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asix electronics corporation release date: 08/18/2007 4f, no. 8, hsin ann rd., hsinchu science park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http:// www.asix.com.tw AX88196BLF low-pin-count non-pci 8/16-bit 10/100m fast ethernet controller with mii interface features document no.: ax88196b_13/08/18/07 high-performance non-pci local bus support 8/16-bit local cpu interfaces include mcs-51 series, 80186 series cpu and isa bus sram-like host interface, easily interfaced to most common embedded mcus embed 8kx16 bits sram for packet buffers support slave-dma to minimize cpu overhead support burst-mode read for highest performance applications interrupt pin with programmable hold-off timer single-chip fast ethernet controller compatible with ieee802.3, 802.3u standards integrate fast ethernet mac/phy transceiver in one chip support 10mbps and 100mbps data rate support full and half duplex operations support 10/100mbps n-way auto-negotiation operation support twisted pair crossover detection and auto-correction (hp auto-mdix) support ieee 802.3x flow control for full-duplex operation support back-pressure flow control for half-duplex operation support vlan match filter provide optional mii interface for external 100base-fx ethernet phy, homepna phy or homeplug phy support wake-on-lan function by following events to reduce power detection of a change in the network link state receipt of a magic packet receipt of a ms wakeup frame ne2000 register level compatible instruction detection performance can be enhanced with only a minor host driver modification from original ne2000 driver support eeprom interface to store mac address ( optional) support up to 2 (out) /1 (in/out) general purpose pins support led pins for various network activity indications integrate voltage regulator and 25mhz crystal oscillator 0.18um cmos process. 3.3v power supply with 5v tolerant i/o pins 100-pin lqfp , rohs package operate over 0 to +70 c temperature range us patent approved (no 6799231) product description the ax88196b is a non-pci ethernet controller with mii for the embedded ethernet applications. the ax88196b supports 8/16-bit sram-like host interface, providing a gl ue-less connection to most common embedded mcus. the ax88196b integrates on-chip fast ethernet mac a nd phy, which is ieee802.3 10base-t and ieee802.3u 100base-tx compatible, and 8kx16 bits embedded sram for packet buffering to accommodate high bandwidth applications. the ax88196b has a wide array of features including support for twisted pair crossover detection and auto-correction, wake-on-lan power management, and ieee 802.3x and b ack-pressure flow control. the programming of ax88196b is simple and compatible with ne2000, so the users don?t need any modification and can easily port the software drivers to many embedded systems very quickly. combining these features with asix?s free tcp/ip software stack for 8-bit microcontrollers, ax 88196b provides the best ethernet solution for embedded networking applications. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electr onics reserves the rights to m odify product speci fication without notice. no liability is assumed as a result of the us e of this product. no rights under any pa tent accompany the sale of the product. ax88196b with mii and 10/100 mbps phy 8bit / 16bit n on-pci bus 51 series / 186 bus series / isa bus general processor ax88196b with mii and 10/100 mbps phy interrupt address csn rdn / wrn data bus mii mii
asix electronics corporation 2 AX88196BLF contents 1.0 introduction............................................................................................................... ....................................... 4 2.0 signal description......................................................................................................... ................................. 6 3.0 memory and csr mapping ..................................................................................................... ..................... 10 4.0 basic operation ............................................................................................................ .................................. 13 5.0 registers operation........................................................................................................ ............................ 31 6.0 cpu read and write functions ............................................................................................... ............... 61 7.0 electrical specification and timings ....................................................................................... ..... 64 8.0 package information ........................................................................................................ ......................... 76 9.0 ordering information ....................................................................................................... ........................ 77 appendix a1: mcs51-like (8-bit)............................................................................................... ....................... 78 appendix a2: isa-like (8/16-bit) .............................................................................................. ......................... 79 appendix a3: 186-like (16-bit)................................................................................................ ........................... 80 appendix a4: co-work with 32-bit processor.................................................................................... . 81 appendix a5: big-endian pr ocessor of data byte lands ............................................................. 83 appendix b: disable ax88196b voltage regulator.......................................................................... 84 reversion history.............................................................................................................. ................................. 85
asix electronics corporation 3 AX88196BLF figures f ig - 1 ax88196b b lock d iagram ............................................................................................................................... .. 4 f ig - 2 ax88196b p in o ut d iagram ............................................................................................................................... 5 f ig - 3 i nternal sram map ............................................................................................................................... ........... 12 f ig - 4 r eceive b uffer r ing ............................................................................................................................... ........... 16 f ig - 5 r eceive b uffer r ing a t i nitialization ........................................................................................................... 17 f ig - 6 tx / rx f low control ............................................................................................................................... ....... 27 f ig - 7 eeprom connections ............................................................................................................................... ........ 29 f ig - 8 pme and irq signal generation ..................................................................................................................... 30 f ig - 9 smi connections ............................................................................................................................... ................. 63 tables t ab - 1 l ocal cpu bus interface signals group ........................................................................................................ 7 t ab - 2 10/100m bps t wisted -p air i nterfaces pins group ........................................................................................... 7 t ab - 3 b uilt - in phy led indicator pins group ......................................................................................................... 7 t ab - 4 eeprom bus interface signals group ............................................................................................................ 7 t ab - 5 miscellaneous pins group ............................................................................................................................... .. 8 t ab - 6 mii pins group ............................................................................................................................... ...................... 9 t ab - 7 eeprom data format example ..................................................................................................................... 10 t ab - 8 csr a ddress m apping ............................................................................................................................... ...... 11 t ab - 9 l ocal m emory m apping ............................................................................................................................... ... 11 t ab - 10 i nternal sram m ap 00h ~ 1fh ................................................................................................................... 11 t ab - 11 i nternal sram m ap 0400h ~ 040fh ........................................................................................................... 11 t ab - 12 b yte l ane m apping ............................................................................................................................... ......... 28 t ab - 13 p ower m anagement s tatuses ...................................................................................................................... 29 t ab - 14 p age 0 of mac c ore r egisters m apping .................................................................................................... 32 t ab - 15 p age 1 of mac c ore r egisters m apping .................................................................................................... 33 t ab - 16 p age 2 of mac c ore r egisters m apping .................................................................................................... 34 t ab - 17 p age 3 of mac c ore r egisters m apping .................................................................................................... 35 t ab - 18 t he e mbedded phy r egisters ...................................................................................................................... 55 t ab - 19 smi m anagement f rame f ormat ................................................................................................................. 63 t ab - 20 mii m anagement f rames - field d escription ............................................................................................. 63
asix electronics corporation 4 AX88196BLF 1.0 introduction 1.1 general description: the ax88196b provides industrial standard ne2000 registers le vel compatible instruction set. various drivers are easily acquired, maintained and no much additional effort is required. software is easily port to various embedded systems with no pain and tears. ax88196b also provides transmit queuing function to enhance standard ne2000 of transmitting performance. the ax88196b fast ethernet controller is a high performance and highly integrated local cpu bus ethernet controller with embedded 10/100mbps phy/transceiver and 8k*16 bit sram. the ax88196b supports both 8/16-bit local cpu interfaces including mcs-51 series , 80186 series, isa bus and high-performance sram-like interface. the simple host interface provides a glue-l ess connection to most common microprocessors and microcontrollers. the ax88196b implem ents both 10mbps and 100m bps ethernet functi on based on ieee802.3 / ieee802.3u lan standard. the ax88196b provides optional mii interface for external 100base-fx ethernet phy, homepna phy or homeplug phy 1.2 ax88196b block diagram: fig - 1 ax88196b block diagram
asix electronics corporation 5 AX88196BLF 1.3 ax88196b pin connection diagram the ax88196b is housed in the 100-pin lqfp package. fig - 2 shows the ax88196b pinout diagram. sa3 sa4 txen txclk txd0 txd1 txd2 txd3 sa5,fifo_sel vcc3io vcck gnd mdio mdc gnd sd0 sd1 sd2 sd3 gnd sd4 sd5 sd6 sd7 gnd 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 sa2 76 50 sd8 sa1 77 49 sd9 nc 78 48 sd10 sa0 79 47 sd11 nc 80 46 sd12 aen,psen 81 45 sd13 nc 82 44 sd14 csn 83 43 sd15 nc 84 42 crs rdn 85 41 col wrn 86 40 gnd iois16 87 39 vcc3io tclk 88 38 vcck test_ck_en 89 37 ireq gnd 90 36 pme nc 91 35 eecs vcck 92 34 eeck nc 93 33 eedio vcc18a 94 32 rxd0 nc 95 31 rxd1 xtalin 96 30 rxd2 nc 97 29 rxd3 xtalout 98 28 gnd nc 99 27 rstn gnd18a 100 ax88196b 26 i_full/col o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 rset_bg nc vcc3a3 nc gnd3a3 nc tpi+ tpi- vcc18a tpo+ tpo- gnd18a v18f vcc3r3 gnd3r3 nc rxclk nc rxdv nc test2 nc test1 i_lk/act i_speed fig - 2 ax88196b pin out diagram
asix electronics corporation 6 AX88196BLF 2.0 signal description the following abbreviations are used in ax88196b pinout tables: all pin names with the ?n? suffix are low-active signals. i input 1.8v o output 1.8v i5 input 3.3v with 5v tolerant o5 output 3.3v with 5v tolerant t5 tri-state with 5v tolerant b5 bi-directional i/ o, 3.3v with 5v tolerant 4m 4ma driving strength 8m 8ma driving strength s schmitt trigger pu internal pull up 75kohm pd internal pull down 75kohm p power pin a analog 2.1 local cpu bus interface signals group signal type pin no. description sa[4:0] i5 74, 75, 76, 77, 79 system address: signals sa[4:0] are address bus input lines. used to select internal csr?s. sa[5] or fifo_sel i5/pd 67 system address or fifo se lect: when driven high, all accesses to the ax88196b are to the rx or tx data buffer fifo (dp). ax88196b supports two kinds of data port for receiving/transmitting packets from/to ax88196b. one is the pio data port (offset 10h); the other one is the sram-like data port (e.g. offset 800h ~ fffh for samsung2440 processor as described in appendix a4 of ax88196b datasheet). the sram-like data port address range depends on which address line of host processor is being connected to the address line sa5/fifo_sel of ax88196b. software on host cpu can issue single data read/write command to both pio data port and sram-like data port. however, to use burst data read/write commands, one has to use sram-like data port, which requires sa5/fifo_sel (pin 45) of ax88196b connecting to an upper address line of host cpu. our reference schematic has sa5/fifo_sel pin connected to upper address line for supporting burst data read/write commands. sd[15:0] b5/8m 43, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 57, 58, 59, 60 system data bus: signals sd[15:0] constitute the bi-directional data bus. irq o5/t5/8m 37 programmable interrupt request. programmable polarity, source and buffer types. can be configure by eeprom auto-loader or btcr (offset 15h) csn i5 83 chip select: active low. rdn i5 85 read: active low strobe to indicate a read cycle. wrn i5 86 write: active low strobe to indicate a write cycle. this signal also used to wakeup the ax88196b when it is in reduced power state. iois16n t5/8m 87 16 bit port: for isa bus used. the iois16n is asserted when the address at the range corresponds to an i/o address to which the chip responds, and the i/o port addressed is capable of 16-bit access. aen or psen i5 81 address enable: when 186, isa mode, this signal is active low to access ax88196b. psen: when 51 modes, this signal is active high to access ax88196b.
asix electronics corporation 7 AX88196BLF pme o5/t5/8m 36 wakeup indicator: when programmed to do so, is asserted when the ax88196b detects a wake event and is requesting the system to wake up from the d1 sleep state. the polarity and buffer type of this signal is programmable by btcr (offset 15h) tab - 1 local cpu bus interface signals group 2.2 10/100mbps twisted-pair interface pins group signal type pin no. description tpi+ ab 7 twisted pair receive input, positive tpi- ab 8 twisted pair receive input, negative tpo+ ab 10 twisted pair transmit output, positive tpo- ab 11 twisted pair transmit output, negative rset_bg ao 1 off-chip resister. must be connected 12.1k ohm 1% to ground. tab - 2 10/100mbps twisted-pa ir interfaces pins group 2.3 built-in phy led indicator pins group signal type pin no. description i_full/col o5/8m 26 full-duplex/collision status. if this signal is low, it indicates full-duplex link established, and if it is high, then the link is in half-duplex mode. when in half- duplex and collision occurrence, the output will be driven low for 80ms and driven high at minimum 80ms. i_speed o5/8m 25 speed status: if this signal is low, it indicates 100mbps, and if it is high, then the speed is 10mbps. i_lk/act o5/8m 24 link status/active: if this signal is low, it indicates link, and if it is high, then the link is fail. when in link status and line activity occurrence, this signal is pulsed high (led off) for 80ms whenever transmit or receive activity is detect ed. this signal is then driven low again for a minimum of 80ms, after which time it will repeat the process if tx or rx activity is detected. tab - 3 built-in phy led indicator pins group 2.4 eeprom signals group signal type pin no. description eecs b5/4m/pd 35 eeprom chip select: eeprom chip select signal. eeprom clock: signal connected to eeprom clock pin. eecs, eeck can load bus type setting during power on reset cycle. eecs eeck bus type 0 0 isa bus / sram-like 0 1 80186 1 0 reserved eeck b5/4m/pd 34 1 1 mcs-51 (805x) eedio b5/4m/pu 33 eeprom data in/out: signal connected to eeprom data input and data output pin. tab - 4 eeprom bus interface signals group
asix electronics corporation 8 AX88196BLF 2.5 miscellaneous pins group signal type pin no. description xtalin i 96 cmos local clock: a 25mhz clock, +/-50 ppm, 40%-60% duty cycle. note that the pin does not support 3.3v or 5v voltage supply. crystal oscillator input: a 25mhz crystal, +/-50 ppm can be connected across xtalin and xtalout. xtalout o 98 crystal oscillator output: a 25mhz crystal, +/-50 ppm can be connected across xtalin and xtal out. if a single-ended external clock (lclk) is connected to xtalin, the crystal output pin should be left floating. rstn i5/s 27 reset: reset is active low then place ax 88196b into reset mode. during the rising edge the ax88196b load s the power on setting data. tclk i5/pd 88 test clock pins: as a clock input for asic testing only no connection when normal operation tclk_en i5/pd/s 89 enable tclk in to asic as a main clock for test only. no connection when normal operation test2 i5/s 21 test mode select connect to ground when normal operation test1 i5/s 23 test mode select connect to ground when normal operation vcc3a3 p 3 power supply for analog circuit: +3.3v dc. gnd3a3 p 5 power supply for analog circuit: +0v dc or ground power. vcc18a p 9, 94 analog power for oscillator, pll, and ethernet phy differential i/o pins, 1.8v gnd18a p 12, 100 analog ground for oscillator, pll, and ethernet phy differential i/o pins. v18f p 13 on-chip 3.3v to 1.8v regulator output +1.8v dc. vcc3r3 p 14 on-chip 3.3v to 1.8v regulator power supply: +3.3v dc. gnd3r3 p 15 on-chip 3.3v to 1.8v regulator ground. gnd p 28, 40, 51, 56, 61, 64, 90 ground. vcc3io p 39, 66 power supply for io: +3.3v dc. vcck p 38, 65, 92 power supply for core logic: +1.8v dc. nc 2, 4, 6, 16, 18, 20, 22, 78, 80, 82, 84, 91, 93, 95, 97, 99 no connection tab - 5 miscellaneous pins group
asix electronics corporation 9 AX88196BLF 2.6 mii pins group signal type pin no. description txclk i/pd 72 transmit clock: txclk is a continuous clock from phy. it provides the timing reference for the transf er of the txen and txd[3:0] signals from the mii port to the phy. txen o5/8m 73 transmit enable: txen is transition synchronously with respect to the rising edge of txclk. txen indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o5/8m 68, 69, 70, 71 transmit data: txd[3:0] is transition synchronously with respect to the rising edge of txclk. for each txclk period in which txen is asserted, txd[3:0] are accepted for transmission by the phy. col i/pd 41 collision: this signal is driven by phy when collision is detected. crs i/pd 42 carrier sense: asynchronous signal crs is asserted by the phy when either transmit or receive medium is non-idle. rxclk i/pd 17 receive clock: rxclk is a continuous clock that provides the timing reference for the transfer of the rxdv and rxd[3:0] signals from the phy to the mii port. rxdv i/pd 19 receive data valid: rxdv is driven by the phy synchronously with respect to rxclk. asserted high when valid data is present on rxd [3:0]. rxd[3:0] i/pd 29, 30, 31, 32 r eceive data: rxd[3:0] is driven by the phy synchronously with respect to rxclk. mdc o5/8m 62 station management data clock: the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdio b5/pu 63 station management data input/output: serial data input/output transfers from/to the phys. tab - 6 mii pins group
asix electronics corporation 10 AX88196BLF 3.0 memory and csr mapping 1. eeprom memory mapping 2. csr mapping 3. local memory mapping 3.1 eeprom memory mapping eeprom interface can access via csr offset 14h smi/eeprom registers when auto load operation completed. the content of eeprom data will be auto-loaded to internal memory from 0000h to 001fh and from 0400h to 040fh automatically when hardware reset. it is similar to ne2000 prom store ethernet address. the real mac address must configured by par0 ~ par5 (cr page1 offset1 ~ offset6). the auto-loader only write to internal sram not write to par0 ~ par5. an example as below, if the desired ethernet physical address is 10-32-54-76-98-ba it is a programmed eeprom if auto-load value is 5 aa5h from eeprom address 0h. after hardware reset the eeprom loader will read first word and check pattern 5aa5h. if the first word value not equal to 5aa5h then the eeprom loader proclaimed that no external eeprom or external eeprom is a non-programmed eeprom. addr bits d[15:8] d[7:0] description 5h [15:0] bah 98h mac address 6 th , 5 th 4h [15:0] 76h 54h mac address 4 th , 3 rd 3h [15:0] 32h 10h mac address 2 nd , 1 st (multicast bit is 1 st of bit_0) [15:11] no define always zero configure internal phy in different ways, such as 10base_t half-duplex mode. if eeprom auto loader not found 5aa5h pattern in first word then internal phy will be not been manual configuration. (default is auto-negotiation enable with all capabilities) [10:8] function 000 auto-negotiation enab le with all capabilities 001 auto-negotiation with 100base-tx fdx / hdx ability 010 auto-negotiation with 10base-t fdx / hdx ability 011 reserved 100 manual selection of 100base-tx fdx 101 manual selection of 100base-tx hdx 110 manual selection of 10base-t fdx [10:8] phy_config 111 manual selection of 10base-t hdx [7:6] no define always zero [5] irq_type_eep this bit will logic or with btcr (15h) bit-5 and will been clear when host write btcr. (offset 15h) [4] irq_pol_eep this bit will logic or with btcr (15h) bit-4 and will been clear when host write btcr. (offset 15h) [3] no define always zero [2] ne2000_prom when set, ax88196b internal memory map of 1ch ~ 1fh will be configured to 57h. an ascii code ?w?. otherwise configured to 42h. an ascii code ?b?. 2h [1:0] no define always zero 1h [15:0] 00h 06h indicates the total of word counts for auto loading 0h [15:0] 5ah a5h programmed pattern tab - 7 eeprom data format example
asix electronics corporation 11 AX88196BLF 3.2 csr mapping system i/o offset function 0000h ~ 001fh ax88196b command status register tab - 8 csr address mapping 3.3 internal sram memory mapping offset function 0000h ~ 001fh load from eeprom 0020h ~ 03ffh reserved 0400h ~ 040fh load from eeprom 0410h ~ 3fffh reserved 4000h ~ 7fffh ne2000 compatible mode 8k x 16 sram buffer 8000h ~ ffffh reserved tab - 9 local memory mapping sram address d[15:8] d[7:0] 1eh 57h / 42h 57h / 42h 1ch 57h / 42h 57h / 42h 1ah ~ 10h 00h 00h 0ah bah bah (e?net address 5) 08h 98h 98h (e?net address 4) 06h 76h 76h (e?net address 3) 04h 54h 54h (e?net address 2) 02h 32h 32h (e?net address 1) 00h 10h 10h (e?net address 0) tab - 10 internal sram map 00h ~ 1fh sram address d[15:8] d[7:0] 40eh 57h 57h 0406h ~ 040dh 00h 00h 0404h bah (e?net address 5) 98h (e?net address 4) 0402h 76h (e?net address 3) 54h (e?net address 2) 0400h 32h (e?net address 1) 10h (e?net address 0) tab - 11 internal sram map 0400h ~ 040fh
asix electronics corporation 12 AX88196BLF ax88196b internal memory address mapping fig - 3 internal sram map page 0x40 (4000h) page 0x7f (7f00h) page 0x80 ( 8000h ) page start (page 0x4c) (4c00h) page 0x4c ( 4c00h ) page stop (page 0x80) (8000h) every page equal to 256 bytes address of first byte in packet buffer sram is page 0x40, offset 0 address of last byte in packet buffer sram is page 0x7f, offset 0xff boundary page start (page 0x4c) current page (page 0x4d) tx page start address (page 0x40) transmit b uffe r receive buffer 0h ~ 1fh, auto load mac address from external eeprom 20h ~ 03ffh, reserved 0400h ~ 040fh, auto load mac address from external eeprom 0410h ~ 3fffh , reserved ( 0000h ) ( 3fffh )
asix electronics corporation 13 AX88196BLF 4.0 basic operation 4.1 receiver filtering the address filtering logic compares the destination addr ess field (first 6 bytes of the received packet) to the physical address registers stored in the address register array. if any one of the six bytes does not match the pre-programmed physical address, the protocol control logic rejects the packet. this is for unicast address filtering. all multicast destination addresses are filtered using a hashing algorithm. (see following description.) if the multicast address indexes a bit that has been set in the filter bit array of the multicast address register array the packet is accepted, otherwise the protocol control logic rejects it. each destin ation address is also checked for all 1?s, which is the reserved broadcast address. 4.1.1 unicast address match filter the physical address registers are used to compare the de stination address of incoming packets for rejecting or accepting packets. comparisons are performed on a byte wi de basis. the bit assignment shown below relates the sequence in par0-par5 to the bit sequence of the received packet. d7 d6 d5 d4 d3 d2 d1 d0 par0 da7 da6 da5 da4 da3 da2 da1 da0 par1 da15 da14 da13 da12 da11 da10 da9 da8 par2 da23 da22 da21 da20 da19 da18 da17 da16 par3 da31 da30 da29 da28 da27 da26 da25 da24 par4 da39 da38 da37 da36 da35 da34 da33 da32 par5 da47 da46 da45 da44 da43 da42 da41 da40 note: the bit sequence of the received p acket is da0, da1, ? da7, da8 ?. 4.1.2 multicast address match filter the multicast address registers provide filtering of multicast addresses hashed by the crc logic. all destination addresses are fed through the 32 bits crc ge neration logic and as the last bit of the destination address enters the crc, the 6 most significant bits of the crc generator are latched. these 6 bits are then decoded by a 1 of 64 decode to index a unique filter bit (fb0-63) in the multicast address registers. if the filter bit selected is set, the multicast packet is accepted. the system designer would use a program to determine whic h filter bits to set in the multicast registers. all multicast filter bits that correspond to multicast address register s accepted by the node are then set to one. to accept all multicast packets all of the registers are set to all ones. d7 d6 d5 d4 d3 d2 d1 d0 mar0 fb7 fb6 fb5 fb 4 fb3 fb2 fb1 fb0 mar1 fb15 fb14 fb13 fb12 fb11 fb10 fb9 fb8 mar2 fb23 fb22 fb21 fb20 fb19 fb18 fb17 fb16 mar3 fb31 fb30 fb29 fb28 fb27 fb26 fb25 fb24 mar4 fb39 fb38 fb37 fb36 fb35 fb34 fb33 fb32 mar5 fb47 fb46 fb45 fb44 fb43 fb42 fb41 fb40 mar6 fb55 fb54 fb53 fb52 fb51 fb50 fb49 fb48 mar7 fb63 fb62 fb61 fb60 fb59 fb58 fb57 fb56
asix electronics corporation 14 AX88196BLF if address y is found to hash to the value 32 (20h), then fb 32 (ref. 4.1.2) in mar2 should be initialized to ``1''. this will cause the ax88196b to accept any multi cast packet with the address y. although the hashing algorithm does not gua rantee perfect filtering of multicast a ddress, it will perfectly filter up to 64 logical address filters if these addresses are chosen to map into unique locations in the multicast filter. note: the first bit of received packet sequen ce is 1?s stands by multicast address. 4.1.3 broadcast address match filter the broadcast check logic comp ares the destination address field (first 6 bytes of the received packet) to all 1?s, which is the values are ?ff ff ff ff ff ff ff? in hex format. if any bit of the six bytes does not equal to 1?s, the protocol control logic rejects the packet. 4.1.4 vlan match filter ax88196b compares the thirteenth a nd fourteenth bytes of receive fra mes. if not match with vlan_id1, vlan_id_0 (offset 1dh, 1ch) then rej ect current frame. the vlan filter will always accept vlan_id is zero of receive frames due to it is 802.1q (for priority purpose) frames. the maximum length of the good packet is thus change from 1518 bytes to 1522 bytes. 32-bit crc generator latch 1 of 64-bit decoder filter bit array x=31 to x=26 clock selected bit 0 = reject, 1= accept 7 bytes preamble sfd 1 byte 6 bytes 6 bytes 2 b 46-1500 bytes 4 bytes destination address source address l/t data pad fcs layer 2 frame (64-1518 bytes) vlan (64-1522 bytes) 8100 tci 2 b 2 b vlan id priority cfi 802.1q vlan tagging 3 bits 12 bits 1 bit
asix electronics corporation 15 AX88196BLF 4.1.5 aggregate address filter with receive configuration setup the final address filter decision depends on the destination address types, id entified by the above 4 address match filters, and the setup of parameters of receive confi guration register. definitions of address match filter result are as following: signal value description phy =1 unicast address match =0 unicast address not match mul =1 multicast address match =0 multicast address not match bro =1 broadcast address match =0 broadcast address not match vid =1 vlan id match =0 vlan id not match agg =1 aggregate address match =0 aggregate address not match the meaning of ab, am and pro signa ls, please refer to ?receive confi guration register? rcr (offset 0ch) the meaning of vlane signal, please refer to ?mac configure register? mcr (offset 1bh) aggregate address filter function will be: ab bro /mul /bro pro mul /bro am phy vlane vid agg
asix electronics corporation 16 AX88196BLF 4.2 buffer management operation there are four buffer memory access types used in ax88196b. 1. packet reception (write data to memory from mac) 2. packet transmission (read data from memory to mac) 3. filling packets to transmit buffer (host fill data to memory) 4. removing packets from the receive bu ffer ring (host read data from memory) the type 1 and 2 operations act as local dma. type 1 does local dma write operation and type 2 does local dma read operation. the type 3 and 4 operations act as remote dma. type 3 does remote dma write operation and type 4 does remote dma read operation. 4.2.1 packet reception the local dma receives channel uses a buffer ring structure comprised of a series of conti guous fixed length 256 byte (128 word) buffers for storage of received packets. the location of th e receive buffer ring is programmed in two registers, a page start and a page stop register. ethernet packets consist of minimum packet size (64 bytes) to maximum packet size (1522 bytes), the 256 byte buffer length provides a good compromise between short packets and longer packets to most efficiently use memory. in addition these buffers provide memory resources for storage of back-to-back packets in loaded networks. buffer management logic in the ax88196b controls the assignment of buffers for storing packets. the buffer management logic provides three basic functions: linki ng receive buffers for long packets, recovery of buffers wh en a packet is rejected, and recalculati on of buffer pages that have been read by the host. at initialization, a portion of the 16k by te (or 8k word) address space is reserv ed for the receiver buffer ring. two eight bit registers, the page start address register (pst art) and the page stop address register (pstop) define the physical boundaries of where the buffers reside. the ax88196b treats the list of buffers as a logical ring; whenever the dma address reaches the page stop addre ss, the dma is reset to the page start address. buffer #1 buffer #2 buffer #3 ? ? ? ? buffer #n physical memory map l ogic receive buffer ring fig - 4 receive buffer ring 4000h 8000h page start page stop 1 2 3 4 ? n-2 n-1 n
asix electronics corporation 17 AX88196BLF initialization of the buffer ring two static registers and two working registers control th e operation of the buffer ring. these are the page start register, page stop register (both described previously ), the current page register and the boundary pointer register. the current page register points to the first buffer used to store a packet and is used to restore the dma for writing status to the buffer ring or for restoring the dma address in the event of a runt packet, a crc, or frame alignment error. the boundary register points to the first packet in the ring not yet read by the host. if the local dma address ever reaches the boundary, reception is a borted. the boundary pointer is also used to initialize the remote dma for removing a packet and is advanced when a packet is removed. a simple analogy to remember the function of these registers is that the current page register acts as a write pointer and the boundary pointer acts as a read pointer. buffer #1 buffer #2 buffer #3 ? ? ? ? buffer #n physical memory map l ogic receive buffer ring fig - 5 receive buffer ring at initialization beginning of reception when the first packet begins arriving the ax88196b and begins storing the packet at the location pointed to by the current page register. an offs et of 4 bytes is reserved in this first bu ffer to allow room for storing receives status corresponding to this packet. linking receive buffer pages if the length of the packet exhausts the first 256 bytes buffer, the dma performs a forward link to the next buffer to store the remainder of the packet. for a maximal length packet the buffer logic will link six buffers to store the entire packet. buffers cannot be skipped when linking; a packet will always be stor ed in contiguous buffers. before the next buffer can be linked, the buffer management logic performs two comparisons. the first comparison tests for equality between the dma address of the next buffer and the contents of the page stop register. if the buffer address equals the page stop register, the buffer management logic will restore the dma to the first buffer in the receive buffer ring value programmed in the page start a ddress register. the second of comparison test between the dma address of the next buffer address and the contents of the boundary pointer register. if the two values are equal the reception is aborted. the bounda ry pointer register can be used to protect against overwriting any area in the receive buffer that has not yet been read. when linking buffers, buffer mana gement will never cross this pointer, effectively avoiding any overwrites. if the buffer address does not match either the boundary pointer or page stop address, the link to the next buffer is performed. 4000h 8000h page start page stop 1 2 3 4 ? n-2 n-1 n boundary page current page
asix electronics corporation 18 AX88196BLF linking buffers before the dma can enter the next c ontiguous 256 bytes buffer, the address is checked for equality to pstop and to the boundary pointer. if neith er is reached, the dma is allo wed to use the next buffer. buffer ring overflow if the buffer ring has been filled and the dma reaches th e boundary pointer address, reception of the current incoming packet will be discard by the ax88196b. thus, the packets previously received and still contained in the ring will not be destroyed. end of packet operations at the end of the packet the ax88196b determines whether the received packet is to be accepted or rejected. it either branch to a rou tine to store the or to another routine that r ecovers the buffers used to store the packet. if current of packet is accepted then ax88196b write two words of buffer header on receive buffer. buffer header description npr, status d[15:8]: next page pointer d[7:6]: always zero d[5]: multicast or broadcast d[4]: runt packet d[3]: mii error d[2]: alignment error d[1]: crc error d[0]: good packet length d[15:11]: always zero d[10:0]: packet length successful reception if the packet is successfully received as shown, the dma is restored to the first buffer used to store the packet (pointed to by the current page regi ster). the dma then stores the receive status, a pointer to where the next packet will be stored and the number of received bytes. note that the remaining bytes in the last buffer are discarded and reception of the next packet begi ns on the next empty 256 byte buffer bounda ry. the current page register is then initialized to the next available buffer in the buffer ring. (the location of the next buffer had been previously calculated and temporarily stored in an internal scratchpad register.) buffer recovery for rejected packets if the packet is a runt packet or contains crc or frame alignment errors, it is rejected. the buffer management logic resets the dma back to the first buffer page used to store the packet (pointed to by cpr), recovering all buffers that had been used to store the rejected packet. this operation w ill not be performed if the ax88196b is programmed to accept either runt pack ets or packets with crc or frame a lignment errors. the received crc is always stored in buffer memory after the la st byte of received data for the packet.
asix electronics corporation 19 AX88196BLF 4.2.2 packet transmission the local dma read is also used duri ng transmission of a packet. three regi sters control the dma transfer during transmission, a transmit page start address register (tpsr) and the transmit byte count registers (tbcr0, 1). when the ax88196b receives a command to tr ansmit the packet pointed to by th ese registers, buffer memory data will be moved into the fifo as required during transm ission. the ax88196b controlle r will generate and append the preamble, synch and crc fields. ax88196b supports options of transmit queue function to enhance transmit performance. original ne2000 of transmit buffer options of transmit buffer as a ring options back-to-back transmission (tx command queue) tpsr tbcr 1, 0 tx page start address (0x40) transmit buffer receive buffer ax88196b remote dma write default operation is continue to write next address even over transmit buffe r area. host can do whole memory read / write testing. and host must handle the transmit data do not overwrite receive buffer area when p erforming fill transmit data to transmit buffer. tx page start address (0x40) transmit buffer receive buffer when active transmit buffe r ring enable (cr page3 o f offset 0dh). ax88196b remote dma write operation will role over from las t transmit page to first transmi t page. host no need reassign rsar0, rsar1 again to fill transmit data for first page. rx page start register, pstart (cr page0, offset 01h) rx page start register, pstart (cr page0, offset 01h) tx command queue push in pop out when active tx queue enable (offset 1bh), host can continue writing txp (bit 2 of c r register) to push tpsr and tbcr1, 0 into ax88196b tx command queue as long as transmit buffer has enough vacancy and ctepr (offse t 1ch) bit7 is ?0?(not full). afte r current packet transmitted completely, mac tx will pop out next tpsr and tbcr1, 0 from tx command queue then transmit this packe t following csma/cd protocol. it is recommended to enable this function to enhance tx performance. ax88196b will report current of transmit end page ctepr (offset 1ch) when every packet transmits completed. host can understand ax88196b current of transmitting buffer point by reading ctepr. mac tx function block
asix electronics corporation 20 AX88196BLF transmit packet assembly the ax88196b requires a contiguous assembled packet with the format shown below. the transmit byte count includes the destination address, source address, length field and data. it does not include preamble and crc. when transmitting data smaller than 64 bytes, ax88196b can auto padding to a minimum length of 64 bytes ethernet frame. the packets are placed in the buffer ram by the system. system programs the ax88196b core's remote dma to move the data from the system buffer ram to internal transmit buffer ram. the data transfer must be 16-bits (1 word) when in 16-bit mode, and 8-bits when the ax88196b controller is set in 8-bit mode. the data width is selected by setting the wts bit in the data configuration register. destination address 6 bytes source address 6 bytes length / type 2 bytes data (pad if < 46 bytes) 46 bytes min. general transmit packet format transmission prior to transmission, the tpsr (transmit page st art register) and tbcr0, tbcr1 (transmit byte count registers) must be initialized. to initiate transmission of th e packet the txp bit in the command register is set. the transmit status register (tsr) is cleared and the ax88196b begins to pre-fetch transmit data from memory. if the inter-packet gap (ipg) has timed out the ax88196b will begin transmission. conditions required to begin transmission in order to transmit a packet, the following three conditions must be met: 1. the inter-packet gap timer has timed out 2. at least one byte has entered the fifo. 3. if a collision had been detected then before transmission the packet back-off time must have timed out. collision recovery during transmission, the buffer management logic monitors the transmit circuitry to determine if a collision has occurred. if a collision is detected, the buffer management logic will reset the fifo and restore the transmit dma pointers for retransmission of the packet. the col bit w ill be set in the tsr and the ncr (number of collisions register) will be incremented. if 15 retransmissions each result in a collision the transmission will be aborted and the abt bit in the tsr will be set.
asix electronics corporation 21 AX88196BLF transmit packet assembly format the following diagrams describe the format for how packets must be assembled prior to transmission for different byte ordering schemes. the various formats are selected in the data configuration register. d15 d8 d7 d0 d[15:8] d[7:0] destination address 1 destination address 0 destination address 3 destination address 2 destination address 5 destination address 4 source address 1 source address 0 source address 3 source address 2 source address 5 source address 4 type / length 1 type / length 0 data 1 data 0 ? ? wts = 1 in data configuration register. this format is used with isa or 80186 mode. d7 d0 destination address 0 (da0) destination address 1 (da1) destination address 2 (da2) destination address 3 (da3) destination address 4 (da4) destination address 5 (da5) source address 0 (sa0) source address 1 (sa1) source address 2 (sa2) source address 3 (sa3) source address 4 (sa4) source address 5 (sa5) type / length 0 type / length 1 data 0 data 1 ? wts = 0 in data configuration register. this format is used with isa or mcs-51 mode. note: all examples above will result in a transmission of a packet in orde r of da0 (destination address 0), da1, da2, da3 and so on in byte. bits within each byte will be transmitted least significant bit first.
asix electronics corporation 22 AX88196BLF 4.2.3 filling packet to transmit buffer (host fill data to memory) the remote dma channel is used to both assembles packet s for transmission, and to remove received packets from the receive buffer ring. it may also be used as a genera l-purpose slave dma channel for moving blocks of data or commands between host memory and local buffer memory. there are two modes of operation, remote write and remote read packet. two register pairs are used to control the remote dma, a remote start address (rsar0, rsar1) and a remote byte count (rbcr0, rbcr1) register pair. the start address register pair point s to the beginning of the block to be moved while the byte count register pair is used to indicate the number of bytes to be transferred. full handshake logic is provided to move data between local buffer memory (embedded memory) and a bi-directional data port. remote write a remote write transfer is used to move a block of data from the host into local buffer memory. the remote dma will read data from the i/o port and sequentially write it to local buffer memory beginning at the remote start address. the dma address will be incr emented and the byte counter will be decremented after each transfer. the dma is terminated when the remote byte count register reaches a count of zero. 4.2.4 removing packets from the ring (host read data from memory) remote read a remote read transfer is used to move a block of data from local buffer memory to the host. the remote dma will sequentially read data from the local buffer memory, beginning at the remote start address, and write data to the i/o port. the dma address will be incremented and th e byte counter will be decr emented after each transfer. the dma is terminated when the remote byte count register reaches zero. packets are removed from the ring using the remote dma or an external device. when using the remote dma. the boundary pointer can also be moved manually by progr amming the boundary register. care should be taken to keep the boundary pointer at least one buffer behind the cu rrent page pointer. the following is a suggested method for maintaining the recei ve buffer ring pointers. 1. at initialization set up a software va riable (next_pkt) to indicate where th e next packet will be read. at the beginning of each remote read dma ope ration, the value of next_pkt will be loaded into rsar0 and rsar1. 2. when initializing the ax88196b set: bnry = pstart cpr = pstart + 1 next_pkt = pstart + 1 3. after a packet is dmaed from the receive buffer ring, the next page poin ter (second byte in ax88196b receive packet buffer header) is us ed to update bnry and next_pkt. next_pkt = next page pointer bnry = next page pointer - 1 if bnry < pstart then bnry = pstop C 1 note the size of the receive buffer ring is reduced by one 256-byte buffer; this will not, however, impede the operation of the ax88196b. the advantage of this scheme is that it easily differentiates between buffer full and buffer empty. it is full when bnry = cpr. it is empty when bnry = cpr-1.
asix electronics corporation 23 AX88196BLF storage format for received packets the following diagrams describe the format for how recei ved packets are placed into memory by the local dma channel. these modes are selected in the data configuration register. d15 d8 d7 d0 next packet pointer receive status receive byte count 1 receive byte count 0 destination address 1 destination address 0 destination address 3 destination address 2 destination address 5 destination address 4 source address 1 source address 0 source address 3 source address 2 source address 5 source address 4 type / length 1 type / length 0 data 1 data 0 ? ? wts = 1 in data configuration register. this format is used with isa or 80186 mode. d7 d0 receive status next packet pointer receive byte count 0 receive byte count 1 destination address 0 destination address 1 destination address 2 destination address 3 destination address 4 destination address 5 source address 0 source address 1 source address 2 source address 3 source address 4 source address 5 type / length 0 type / length 1 data 0 data 1 ? wts = 0 in data configuration register. this format is used with isa or mcs-51 mode.
asix electronics corporation 24 AX88196BLF 4.2.5 other useful operations memory diagnostics memory diagnostics can be achieved by remote write/read dma operations. the following is a suggested step for memory test and assume the ax88196b has been well initialized. 1. issue the stop command to the ax88196b. this is accomplished be setting the stp bit in the ax88196b's command register. writing 21h to the command register will stop the ax88196b. 2. wait for at least 1.5 ms. since the ax88196b will comple te any reception that is in progress, it is necessary to time out for the maximum possible duration of an et hernet reception. this action prevents buffer memory from written data through local dma write. 3. write data pattern to mut (memory under test) by remote dma write operation. 4. read data pattern from mut (memory under test) by remote dma read operation. 5. compare the read data pattern with original write data pattern and check if it is equal. 6. repeat step 3 to step 5 with various data pattern. loop-back diagnostics 1. issue the stop command to the ax88196b. this is accomplished be setting the stp bit in the ax88196b's command register. writing 21h to the co mmand register will stop the ax88196b. 2. wait for at least 1.5 ms. since the ax88196b will comple te any reception that is in progress, it is necessary to time out for the maximum possible duration of an et hernet reception. this action prevents buffer memory from written data through local dma write. 3. place the ax88196b in mode 1 loop-back. (mac inte rnal loop-back) this can be accomplished by setting lb1 and lb0, of the transmit configuration register to ``0,1''. 4. issue the start command to the ax88196b. this can be accomplished by writing 22h to the command register. this is necessary to activate the ax88196b's remote dma channel. 5. write data that want to transmit to transmit buffer by remote dma write operation. 6. issue the txp command to the ax88196b. this can be accomplished by writing 26h to the command register. 7. read data current receive buffe r by remote dma read operation. 8. compare the received data with original transmit data and check if it is equal. 9. repeat step 5 to step 8 for more packets test.
asix electronics corporation 25 AX88196BLF 4.3 wake-up detection setting wake up control and status wucs (cr page3, o ffset 0ah) and d1 power saving in power management register pmr (cr page3, offset 0b h), place the ax88196b in wake on lan de tection mode. in this mode, normal data reception is disabled. and detec tion logic within the mac examines r eceive data for three kinds of wol events. - examines receive data for the pre-programmed wake-up frame patterns - examines receive data for the magic packet frame patterns - examines phy link status change 4.3.1 wake-up frame ax88196b supports four programmable filters that support ma ny different receive packet patterns. if the remote wakeup mode is enable (in d1 sleep state). the remote wakeup function receives all frames and checks each frame against the enabled filter and recognizes the frame as a re mote wake-up frame if it passes the mac address filtering and crc value match. in order to determine which byte s of the frames should be checked by the crc-16 (x16 +x15 +x2 +1) module. ax88196b use a programma ble byte mask and a programmable pa ttern offset for each of the four supported filters. ax88196b also provide last byte match check and options cascade four programmable filters. make the four of detectors can operate simultaneously or sequentially. the byte mask is a 32-bit field that specifies whether or not each of th e 32 contiguous bytes within the frame, beginning in the pattern offset, should be checked. if bit j in the byte mask is set, the diction logic checks byte offset +j in the frame. the pattern offset define on offset 3 ~ 0 for each wake-up filter 3 ~ 0 and the real offset value equal to offset register multiplied by 2. (for example, the real offset value equal to 12 if set 6 on offset register field) last bytes 3 ~ 0 for each wake-up filter 3 ~ 0 also. the contents of last byte register must equal to the last of byte mask bit indicates of byte value. for example, if set byte mask [31:0] as 00c30003h then byte mask [23] is the last byte. thus, the contents of last byte register must equal to byte value of offset + 23. in order to load the 32-bits of wake up control register hos t driver software must perform 4 writes for every 32 bit of registers. the first write of 8-bit is located at [ 31:24]. the second write will also occupy [ 31:24] and shift the first write of data to [23:16]. the first write of data will be located at [7:0] after continue 4 times of write data. 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 byte mask 0 byte mask 1 byte mask 2 byte mask 3 wakeup frame 1 crc wakeup frame 0 crc wakeup frame 3 crc wakeup frame 2 crc offset 3 offset 2 offset 1 offset 0 last byte 3 last byte 2 last byte 1 last byte 0 reserved cascade command [2:0] command 3 command 2 command 1 command 0 wake-up frame byte mask register structure 4 th [31:24] 3 r d [23:16] 2 n d [15:8] 1 s t [7:0]
asix electronics corporation 26 AX88196BLF . for example. a ping packet is configured as a wakeup frame and ax88196b mac address is 00 a0 0c c4 7d 69. 00 a0 0c c4 7d 69 00 0e c6 12 34 56 08 00 45 00 00 3c 01 8c 00 00 80 01 27 1e c0 09 c9 02 c0 09 c9 01 08 00 47 5c 05 00 01 00 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 61 62 63 64 65 66 67 68 69 crc (4 bytes) host configure wakeup frame registers sequences // go to gape3 write cr(offset 0h) c2h ; page3 // set byte mask 0 = 00 40 08 07 write wfbm0 (page3, offset 01h) 07h ; wfbm0 = 07 00 00 00h write wfbm0 (page3, offset 01h) 08h ; wfbm0 = 08 07 00 00h write wfbm0 (page3, offset 01h) 40h ; wfbm0 = 40 08 07 00h write wfbm0 (page3, offset 01h) 00h ; wfbm0 = 00 40 08 07 h // set {wakeup frame 1 crc, wakeup frame 0 crc} = 00 00 2b 42 h write wf10crc (offset 05h) 42h ; wf10crc = 42 00 00 00h write wf10crc (offset 05h) 2bh ; wf10crc = 2b 42 00 00h write wf10crc (offset 05h) 00h ; wf10crc = 00 2b 42 00h write wf10crc (offset 05h) 00h ; wf10crc = 00 00 2b 42 h // set {offset 3 2 1 0} = 00 00 00 06h write wfofst (offset 07h) 06h ; wfofst = 06 00 00 00h write wfofst (offset 07h) 00h ; wfofst = 00 06 00 00h write wfofst (offset 07h) 00h ; wfofst = 00 00 06 00h write wfofst (offset 07h) 00h ; wfofst = 00 00 00 06 h (offset = 6*2 = 12) // set {last byte 3 2 1 0} = 00 00 00 08h write wflb (page3, offset 08h) 08h ; {last byte 3 2 1 0} = 08 00 00 00h write wflb (page3, offset 08h) 00h ; {last byte 3 2 1 0} = 00 08 00 00h write wflb (page3, offset 08h) 00h ; {last byte 3 2 1 0} = 00 00 08 00h write wflb (page3, offset 08h) 00h ; {last byte 3 2 1 0} = 00 00 00 08 h // set {cascade, command 3 2 1 0} = 00 00 00 03h write wfcmd (offset 09h) 03h ; wfcmd = 03 00 00 00h write wfcmd (offset 09h) 00h ; wfcmd = 00 03 00 00h write wfcmd (offset 09h) 00h ; wfcmd = 00 00 03 00h write wfcmd (offset 09h) 00h ; wfcmd = 00 00 00 03 h (enabled wake-up frame filter 0, and da match is required) // set pme and irq pin i/o buffer type (pleas e ref. datasheet offset 15 descriptions) write btcr (offset 15h) ; // host enables wakeup frame de tection then enter d1 sleep write wucsr (page3, offset 0ah) 02h ; (wakeup frame enable) write pmr (offset 0bh) 01h ; (enter d1 sleep mode) 4.3.2 magic packet frame ax88196b checks frame for 16 repetitions of the mac a ddress without any breaks or interruptions. the 16 repetitions may be anywhere in the frame but mu st be preceded by the synchronization stream 48?hff_ff_ff_ff_ff_ff pattern. if the mac address of a node is 00h 11h 22h 33h 44h 55h, then ax88196b scans for the following data sequence in an ethernet frame. destination address (6 byte) source address (6 byte) . . . . . . . . . ff ff ff ff ff ff 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 . . . . . . . . . crc (4 byte)
asix electronics corporation 27 AX88196BLF 4.4 flow control the ax88196b supports full-duplex flow control using the pa use control frame. it also supports half-duplex flow control using collision base of back-pressure method. 4.4.1 full-duplex flow control the format of a pause frame is illustrated below. it confor ms to the standard ethernet frame format but includes a unique type field and other parameters as follows: the destination address of the frame may be set to either th e unique da of the station to be paused, or to the globally assigned multicast address 01-80-c2-00-00-01 (hex). the ieee 802.3 standard for use in mac control pause frames has reserved this multicast address. the "type" fiel d of the pause frame is set to 88-08 (hex) to indicate the frame is a mac control frame. the mac control opcode field is set to 00-01 (hex) to indicate the type of mac control frame being used is a pause frame. the pause frame is the only type of mac control frame currently defined. the mac control parameters field contains a 16-bit value that specifies the duration of the pause event in units of 512-bit times. valid values are 00-00 to ff-ff (hex). if an additional pause frame a rrives before the current pause time has expired, its parameter replaces the curre nt pause time, so a pause frame with parameter zero allows traffic to resume immediately. a 42-byte reserved field (transmitted as all zeros) is required to pad the length of the pause frame to the minimum ethernet frame size. preamble (7-bytes) start frame delimiter (1-byte) dest. mac address (6-bytes) = (01-80-c2- 00-00-01) source mac address (6-bytes) length/type (2-bytes) = 802.3 mac control (88-08) mac control opcode (2-bytes) = pause (00-01) mac control parameters (2-bytes) = (00-00 to ff-ff) reserved (42-bytes) = all zeros frame check sequence (4-bytes) ax88196b will inhibit transmit frames for a specified pe riod of time if a pause frame received and crc is correct. if a pause request is received while a transmit frame is in progress, then the paus e will take effect after the transmitting is completed. ax88196b base on ?rx page start register? (cr page0 offs et 01h) and ?rx page stop register?(cr page0 offset 02h) to calculate and got the total of free page count can be used for store received pack ets. (one page equal to 256 bytes) the total of free page count will decrease when packets received. a programmable of high water free-page-count in ?flow control regist er? (offset 1ah) used to measure the water level of receive buffer. ax88196b use xoff / xon flow-control me thod to avoid missing packet if receive buffer almost full. a xon transmitting when the total of free page count equal to or less then ?high water free-page-count?. a xoff transmitting when the total of free page count equal to or greater then (?high water free-page-count? + 6 pages). fig - 6 tx / rx flow control rx pause frame tx host packet stop ax88796b tx flow control rx flow control the total of free pages count programmable of free-page-count start to generate xon frame packet generate xoff frame packet high water mark low water mark packets in rx buffer 6 pages
asix electronics corporation 28 AX88196BLF 4.4.2 half-duplex flow control whenever the receive buffer becomes fu ll crosses a certain threshold level, the mac starts sending a jam signal, which will result in a collision. after sensing the collision, the remote station will back off its transmit ion. ax88196b only generate this collision-based of back-pressure when it receives a new frame, in order to avoid any late collisions. a programmable of ?back-pressure jam li mit count? (offset 17h) is used for avoid hub port partition due to many continues of collisions. ax88196b will reset the ?back-pre ssure jam limit count? when either a transmitted or received frame without collision. a back -pressure leakage allow when senses continue of collisions count up to ?back-pressure jam limit count?, it will be no jamming one of receive frame even receive buffer is full. 4.5 big- and little-endian support ax88196b supports ?big-? or ?little-endian ? processor. to support big-endian processors, the hardware designer must explicitly invert the layout of the byte lanes. in addition, for a 16-bit inte rface, the big-endian register must be set correctly following the table below. additionally, please refer to big-endian register (offset 1e h), for additional information on status indication on big- or little-endian modes. mode ofoperation ax88196b data pins description sd[15:8] sd[7:0] mode 0 big-endian register (offset 1eh) not equal to 0x0000h even access byte3 byte2 odd access byte1 byte0 this mode can be used by 32-bit processors operating with an external 16-bit bus. mode 0 little-endian register (offs et 1eh) equal to 0x0000h (default) even access byte1 byte0 odd access byte3 byte2 this mode can also be used by native 16-bit processors. tab - 12 byte lane mapping ax88196b?s 16-bit data port (dp) read /write like a fifo not rely on addr ess pin. the ?even access? means the first of access data port (dp) behind of remote read /write command register (cr). the second time access data port (dp) is ?odd access? and then next is ?even access?, and so on. host can read bit-7 in ?device status register? (offset 17h) to know the curre nt of big- or little-endian types. the default is little-endian mode. 4.6 general purpose timer (gp timer) the programmable general purpose timer can be used to ge nerate periodic host interrupts and the resolution of this timer is 100us. the gp timer is a 16-bit of register. gpt1 (cr page3 offset 0fh) and gpt0 (cr page3 offset 0eh) to compost this 16-bit of general purpose timer. this gp timer field of default value is ffffh. once set the general purpose timer enable (cr page3 offset 0dh) the gpt counts down until it reaches 0000h then update the a new pre-load value into gpt, and continues counting. the gpt interrupt has no status indicate in interrupt status register (cr page 0 offset 07h). the interrupt event will keep active until host driver r ead interrupt status register (cr page0 o ffset 07h) then clear gpt interrupt event.
asix electronics corporation 29 AX88196BLF 4.7 eeprom interface ax88196b can optionally load its mac address from an external serial eeprom. if a properly configured eeprom is detected by ax88196b at power-up, hard reset or host set a reload eeprom request (cr page3 offset 0ch), the constants of eeprom data will be auto lo ading to internal memory from 0000h to 001fh and from 0400h to 040fh automatically. it is similar ne2000 prom store mac address field. a detailed explanation of the eeprom data format in section 3.1 ?eeprom memory mapping?. after auto load eeprom completed not indicate ax88196b knew its mac address. host driver can get mac address from internal memory (0000h ~ 001fh) or (0400h ~ 040fh) and write ?physical address registers? (cr page1 offset 01h ~ 06h). the ax88196b eeprom use 3 pin to connect to a most ?93c46? type eeprom configured for x16-bit operation. a connect diagram as below fig - 7 eeprom connections after eeprom loader has finished reading the mac after power-on, hard reset or host set a reload eeprom request (cr page3 offset 0ch), the host is free to pe rform eecs, eeck and eedio as general purpose i/o pin. 4.8 power management ax88196b supports power-down modes to allow applicati ons to minimize power consumption. there is one normal operation power state, d0 and there are two power saving states: d1, and d2. the ?power management register?(cr page3 offset 0bh) controls those of power management modes. in d1 power saving state, ax88196b supports wake on lan function. in d2 power saving state, ax88196b will off all function block and clocks to minimize power consumption. after wakeup event, the ?power management register? will be cleared and state at normal operation power state. when ax88196b in either d1 or d2 power saving mode, host can write ?host wake up register? (offset 1fh) return the ax88196b to the d0 state. power is reduced to various modules by disabling the clocks as outlined in table as below. ax88196b block d0 (normal operation) d1 (wol) d2 internal clock on on off mac and host on off off mac power management on rx block on off phy on on off tab - 13 power management statuses eecs eec k eedio ax88196b eecs eeck eedi eedo 93c46
asix electronics corporation 30 AX88196BLF 4.8.1 power management event indicators the external pme signal can be setup as push-pull driver or open-drain buffer. and also can be set as active high or active low. when set the pme_ ind bit to a ?1?, (offset 15h) the external pme signal will be driven active for 60ms upon detection of a wake-up event. when the pme_ind bit is cleared, the pme signal w ill be driven continuously upon detection of a wake-up event. host can checks wh ich kind of wake-up event activity by reads ?wake up control and status register?(cr page3 offset 0ah). host can writing ?power management register?(cr page3 offset 0bh) or writing a ?1? to clear wake-up event activity flags on ?wake up control and status register?(cr page3 offset 0ah) to deactivated pme signal. mpen (cr page3 offset 0ah) enb pme logic pme_pol (offset 15h) pme_type (offset 15h) wuen (cr page3 offset 0ah) magic packet detect event wakeup frame detect event enb logic ireq irq_type (offset 15h) irq_pol (offset 15h) system interrupt event pme_irq_en (offset 15h) irq_type (from eeprom) irq_pol (from eeprom) pme_ind (offset 15h) 60ms fig - 8 pme and irq signal generation 4.9 device ready or busy there are three kinds of device ready indicator in ?dev ice status register? (offset 17h). those are indicates ax88196b internal operation busy. in order to prevent the host access ax88196b in the busy stage, host can to check the ?device status register? before doing some key operations. when a ?0? at the bit-4 (d-rdy) in ?device status register? (offset 17h), indicate the ax88196b in reset state or power saving state or eeprom loading state or loop-back mode swapping. when a ?0? at the bit-5 (rd-rdy) in ?device status register? (offset 17h), indicate the remote-dma-read data not ready yet, host must not read data port (dp) in this period. the non-ready period only happen when host set a remote-read command on ?command register?(cr), and it will be go to ready state when a valid data pop out for host to reading. host driver can b ack-to-back read data port (dp) sin ce checked the rd-rdy was ready. the maximum of remote-read non-ready period only spend 60ns . host can ignore to check rd_rdy if host access time not faster then it. when a ?0? at the bit-6 (rdma-rdy) in ?device status register? (offset 17h), indicate the remote dma not completed yet. this rdma-rdy will be cleared when host write ?remot e byte count 0? rbcr0 (cr page0 offset 0ah) or ?remote byte count 1? rbcr1 (cr page0 offset 0bh). the byte counter will down counting when every data port (dp) access. this rdma-rdy will be set when byte counter count to zero.
asix electronics corporation 31 AX88196BLF 5.0 registers operation 5.1 mac control and status registers (csr) all registers of mac core are 8-bit wide except data port (dp). data port is optional 8 or 16-bit wide by wts (dcr). offset 01h to 0fh mapped into pages, which are selected by ps (page select) in the command register. offset page0 page1 page2 page3 00h command register (cr) 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h, 11h data port (dp) 12h inter-frame gap segment 1 (ifgs1) 13h inter-frame gap segment 2 (ifgs2) 14h mii/eeprom access 15h buffer type configure register (btcr) 16h inter-frame gap (ifg) 17h device status register (dsr) / back-pressure jam limit count (bjlc) 18h max frame size [7:0] 19h max frame size [11:8] 1ah flow control register (fcr) 1bh mac configure register (mcr) 1ch current tx end page register (ctepr) / vlan_id_0 1dh reserved / vlan_id_1 1eh reserved / big-endian register (ber) 1fh software reset / host wake up (hwake) page0 of registers page1 of registers page2 of registers page3 of registers
asix electronics corporation 32 AX88196BLF page 0 (ps1=0,ps0=0) offset read write 00h command register (cr) command register (cr) 01h rx page start register (pstart) page start register (pstart) 02h rx page stop register (pstop) page stop register (pstop) 03h boundary pointer (bnry) boundary pointer (bnry) 04h transmit status register (tsr) transmit page start address (tpsr) 05h number of collisions register (ncr) transmit byte count register 0 (tbcr0) 06h current page register (cpr) transmit byte count register 1 (tbcr1) 07h interrupt status register (isr) interrupt status register (isr) 08h current remote dma address 0 (crda0) remote start address register 0 (rsar0) 09h current remote dma address 1 (crda1) remote start address register 1 (rsar1) 0ah reserved remote byte count 0 (rbcr0) 0bh reserved remote byte count 1 (rbcr1) 0ch receive status register (rsr) receive configurati on register (rcr) 0dh frame alignment error tally register (cntr0) transmit configuration register (tcr) 0eh crc error tally register (cntr1) data configuration register (dcr) 0fh frames lost tally register (cntr2) interrupt mask register (imr) 11h, 10h data port (dp) data port (dp) 12h inter-frame gap segment 1 (ifgs1) inter-frame gap segment 1 (ifgs1) 13h inter-frame gap segment 2 (ifgs2) inter-frame gap segment 2 (ifgs2) 14h mii/eeprom access mii/eeprom access 15h buffer type configure register (btcr) buffer type configure register (btcr) 16h inter-frame gap (ifg) inter-frame gap (ifg) 17h device status register (dsr) back-pressure jam limit count (bjlc) 18h max frame size [7:0] max frame size [7:0] 19h max frame size [11:8] max frame size [11:8] 1ah flow control register (fcr) flow control register (fcr) 1bh mac configure register (mcr) mac configure register (mcr) 1ch current tx end page register (ctepr) vlan_id_0 1dh reserved vlan_id_1 1eh reserved big-endian register (ber) 1fh software reset host wake up (hwake) tab - 14 page 0 of mac core registers mapping
asix electronics corporation 33 AX88196BLF page 1 (ps1=0,ps0=1) offset read write 01h physical address register 0 (par0) physical address register 0 (par0) 02h physical address register 1 (par1) physical address register 1 (par1) 03h physical address register 2 (par2) physical address register 2 (par2) 04h physical address register 3 (par3) physical address register 3 (par3) 05h physical address register 4 (par4) physical address register 4 (par4) 06h physical address register 5 (par5) physical address register 5 (par5) 07h current page register (cpr) current page register (cpr) 08h multicast address register 0 (mar0) multicast address register 0 (mar0) 09h multicast address register 1 (mar1) multicast address register 1 (mar1) 0ah multicast address register 2 (mar2) multicast address register 2 (mar2) 0bh multicast address register 3 (mar3) multicast address register 3 (mar3) 0ch multicast address register 4 (mar4) multicast address register 4 (mar4) 0dh multicast address register 5 (mar5) multicast address register 5 (mar5) 0eh multicast address register 6 (mar6) multicast address register 6 (mar6) 0fh multicast address register 7 (mar7) multicast address register 7 (mar7) tab - 15 page 1 of mac core registers mapping
asix electronics corporation 34 AX88196BLF page 2 (ps1=1,ps0=0) offset read write 01h reserved reserved 02h reserved reserved 03h reserved reserved 04h reserved reserved 05h reserved reserved 06h reserved reserved 07h reserved reserved 08h reserved reserved 09h reserved reserved 0ah total receive buffer free page (tfp) reserved 0bh chip version (00h) reserved 0ch receive configurati on register (rcr) reserved 0dh transmit configuration register (tcr) reserved 0eh data configuration register (dcr) reserved 0fh interrupt mask register (imr) reserved tab - 16 page 2 of mac core registers mapping
asix electronics corporation 35 AX88196BLF page 3 (ps1=1,ps0=1) offset read write 01h wfbm0 wfbm0 02h wfbm1 wfbm1 03h wfbm2 wfbm2 04h wfbm3 wfbm3 05h wf10crc wf10crc 06h wf32crc wf32crc 07h wfofst wfofst 08h wflb wflb 09h wfcmd wfcmd 0ah wucsr wucsr 0bh pmr pmr 0ch reserved reer 0dh misc misc 0eh gpt0 gpt0 0fh gpt1 gpt1 tab - 17 page 3 of mac core registers mapping
asix electronics corporation 36 AX88196BLF 5.1.1 command register (cr) offset 00h (read/write) field name description (default = 21h) 7:6 ps1, ps0 ps1, ps0: page select the two bits select which regist er?s page is to be accessed. it will be reset to default value when set pmr to d1 to d2 sleep state. ps1 ps0 0 0 page 0 (default) 0 1 page 1 1 0 page 2 1 1 page 3 5:3 rd2, rd1, rd0 rd2, rd1, rd0: remote dma command these three encoded bits control operation of the remote dma channel. rd2 could be set to abort any remote dma command in process. rd2 is reset by ax88196b when a remote dma has been completed. the remote byte count should be cleared when a remote dma has been aborted. the remote start address is not restored to the starting address if the remote dma is aborted. it will be reset to default value when set pmr to d1 to d2 sleep state. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 not allowed 1 x x abort / complete remote dma (default) 2 txp txp: transmit packet this bit could be set to initiate transmission of a packet 1 start start: this bit is used to active ax88196b operation. this bit always read high when host set once. it only clear by hardware or software reset. 0 stop stop: stop ax88196b this bit is used to stop the ax88196b operation. it will be reset to default value when set pmr to d1 to d2 sleep state.
asix electronics corporation 37 AX88196BLF 5.1.2 rx page start register (pstart) page0 offset 01h (read/write) field name description (default = 00h) 7:0 pstart receive buffer ri ng page start register 5.1.3 rx page stop register (pstop) page0 offset 02h (read/write) field name description (default = 00h) 7:0 pstop receive buffer ri ng page stop register 5.1.4 boundary pointer (bnry) page0 offset 03h (read/write) field name description (default = 4ch) 7:0 bnry boundary page pointer 5.1.5 transmit page start address (tpsr) page0 offset 04h (write) field name description 7:0 tpsr transmit page start address 5.1.6 transmit status register (tsr) page0 offset 04h (read) field name description (default = 00h) 7 owc out of window collision 6:4 - reserved 3 abt transmit aborted indicates the ax88196b aborted transmi ssion because of excessive collision. 2 col transmit collided indicates that the transmission collided at least once with another station on the network. 1 - reserved 0 ptx packet transmitted indicates transmission without error. 5.1.7 transmit byte count register (tbcr0) page0 offset 05h (write) field name description 7:0 tbcr0 transmit byte count register . the bit assignment is shown below
asix electronics corporation 38 AX88196BLF 5.1.8 number of collisions register (ncr) page0 offset 05h (read) field name description (default = 00h) 7:4 - always zero 3:0 ncr if no collisions are experienced during a tr ansmission attempt, the col bit of the tsr will not be set and the contents of ncr will be zero. if there are excessive collisions, the abt bit in the tsr will be set and the contents of n cr will be zero. the ncr is cleared after the txp bit in the cr is set. 5.1.9 transmit byte count register (tbcr1) page0 offset 06h (write) field name description 7:0 tbcr1 transmit byte count register. 5.1.10 current page register (cpr) page0 offset 06h (read) field name description (default = 4dh) 7:0 cpr the buffer management logic as a bac kup register for reception uses this register internally. curr contains the address of the fi rst buffer to be used for a packet reception and is used to restore dma pointers in the event of receive errors. this register is initialized to the same value as pstart and should not be written to again unless the controller is reset. 5.1.11 interrupt status register (isr) page0 offset 07h (read/write) field name description (default = 80h) 7 rst reset status: set when ax88196b enters reset state (or a wake-up event) and cleared when a start command is issued to the cr. writing to this bit is no effect. 6 rdc remote dma complete set when remote dma operation has been completed. write this bit to high then reset it. 5 cnt counter overflow set when msb of one or more of the tally counters has been set. write this bit to high then reset its. 4 ovw overwrite: set when receive buffer ring storage resources have been exhausted. write this bit to high then reset it. 3 txe transmit error set when packet transmitted with one or more of the following errors excessive collisions, transmit over size and late collision. write this bit to high then reset it. 2 rxe receive error indicates that a packet was received w ith one or more of the following errors crc error frame alignment error missed packet write this bit to high then reset it. 1 ptx packet transmitted indicates packet transmitted with no error write this bit to high then reset it. 0 prx packet received indicates packet received with no error. write this bit to high then reset it.
asix electronics corporation 39 AX88196BLF remote dma operations are programmed via the remote start address (rsar0, 1) and remote byte count (rbcr0, 1) registers. 5.1.12 remote start address register (rsar0) page0 offset 08h (write) field name description 7:0 rsar0 the remote start address is used to point to the start of the block of data to be transferred. 5.1.13 remote start address register (rsar1) page0 offset 09h (write) field name description 7:0 rsar1 the remote start address is used to point to the start of the block of data to be transferred. 5.1.14 remote byte count register (rbcr0) page0 offset 0ah (write) field name description 7:0 rbcr0 the remote byte count is used to indicate the length of the block (in bytes). 5.1.15 remote byte count register (rbcr1) page0 offset 0bh (write) field name description 7:0 rbcr1 the remote byte count is used to indicate the length of the block (in bytes). 5.1.16 current remote dma address (crda0) page0 offset 08h (read) field name description (default = 00h) 7:0 crda0 the current remote dma registers contain the current address of the remote dma. the bit assignment is shown below: 5.1.17 current remote dma address (crda1) page0 offset 09h (read) field name description (default = 00h) 7:0 crda1 the current remote dma registers contain the current address of the remote dma. the bit assignment is shown below:
asix electronics corporation 40 AX88196BLF 5.1.18 receive configuration register (rcr) page0 offset 0ch (write) field name description 7 - reserved 6 - reserved 5 mon monitor mode 0: normal operation. (default) 1: monitor mode, the input packet will be checked on node address and crc but not buffered into memory. 4 pro pro: promiscuous mode enable the receiver to accept all p ackets with a physical address. 3 am am: accept multicast enable the receiver to accept p ackets with a multicast address. that multicast address must pass the hashing array. 2 ab ab: accept broadcast enable the receiver to accept broadcast packet. 1 ar ar: accept runt enable the receiver to accept runt packet. 0 sep sep: save error packet enable the receiver to accept a nd save packets with error. 5.1.19 receive status register (rsr) page0 offset 0ch (read) field name description (default = 00h) 7 - reserved 6 dis receiver disabled 5 phy multicast address received. 4 mpa missed packet 3 - always zero 2 fae frame alignment error. 1 cr crc error. 0 prx packet received intact
asix electronics corporation 41 AX88196BLF 5.1.20 transmit configuration register (tcr) page0 offset 0dh (write) field name description 7 fdu full duplex this bit configure mac media mode is full duplex or not. 0: half duplex (default) 1: full duplex this duplex setting was wire or with mcr bit- 7. each one goes high then configures mac as full-duplex. ax88196b will ignore this bit a nd mcr bit-7 when using internal phy. 6 pd pad disable 0: pad will be added when packet length less than 60. (default) 1: pad will not be added when packet length less than 60. 5 rlo retry of late collision 0: don?t retransmit packet when late collision happens. (default) 1: retransmit packet when late collision happens. 4:3 - reserved 2:1 lb1, lb0 encoded loop-back control these encoded configuration bits set the type of loop-back that is to be performed. lb1 lb0 mode0 0 0 normal operation (default) mode 1 0 1 internal ax88196b loop-back mode 2 1 0 phy loop-back no define 1 1 reserved 0 crc inhibit crc 0: crc appended by transmitter. (default) 1: crc inhibited by transmitter. 5.1.21 frame alignment error tally register (cntr0) page0 offset 0dh (read) field name description (default = 00h) 7:0 cntr0 this counter is incremented every time a packet is received with a frame alignment error. the packet must have been recognized by th e address recognition logic. the counter is cleared after the pr ocessor reads it. 5.1.22 data configuration register (dcr) page0 offset 0eh (write) field name description 7:2 - reserved 1 - reserved 0 wts word transfer select (data port only) 0: selects data port with byte-wide transf ers. (default) 1: selects data port with word-wide transfers. 5.1.23 crc error tally register (cntr1) page0 offset 0eh (read) field name description (default = 00h) 7:0 cntr1 this counter is incremented every time a packet is received with a crc error. the packet must first be recognized by th e address recognition logic. the counter is cleared after the processor reads it.
asix electronics corporation 42 AX88196BLF 5.1.24 interrupt mask register (imr) page0 offset 0fh (write) field name description 7 reserved 6 rdce dma complete interrupt enable. default ?low? disabled. 5 cnte counter overflow interrupt enable. default ?low? disabled. 4 ovwe overwrite interrupt enable. default ?low? disabled. 3 txee transmit error interrupt enable. default ?low? disabled. 2 rxee receive error interrupt en able. default ?low? disabled. 1 ptxe packet transmitted interrupt enable. default ?low? disabled. 0 prxe packet received interrupt enable. default ?low? disabled. 5.1.25 frames lost tally register (cntr2) page0 offset 0fh (read) field name description (default = 00h) 7:0 cntr2 this counter is incremente d if a packet cannot be received due to lack of buffer resources. in monitor mode, this counter will count the number of packets that pass the address recognition logic.
asix electronics corporation 43 AX88196BLF 5.1.26 physical address register 0 (par0) page1 offset 01h (read/write) field name description (default = 00h) 7:0 par0 physical address register 0 5.1.27 physical address register 1 (par1) page1 offset 02h (read/write) field name description (default = 00h) 7:0 par1 physical address register 1 5.1.28 physical address register 2 (par2) page1 offset 03h (read/write) field name description (default = 00h) 7:0 par2 physical address register 2 5.1.29 physical address register 3 (par3) page1 offset 04h (read/write) field name description (default = 00h) 7:0 par3 physical address register 3 5.1.30 physical address register 4 (par4) page1 offset 05h (read/write) field name description (default = 00h) 7:0 par4 physical address register 4 5.1.31 physical address register 5 (par5) page1 offset 06h (read/write) field name description (default = 00h) 7:0 par5 physical address register 5 the physical address registers are used to compare the de stination address of incoming packets for rejecting or accepting packets. comparisons are performed on a byte wi de basis. the bit assignment shown below relates the sequence in par0 ~ par5 to the b it sequence of the received packet.
asix electronics corporation 44 AX88196BLF 5.1.32 current page register (cpr) page1 offset 07h (read/write) field name description (default = 4dh) 7:0 cpr the buffer management logic as a bac kup register for reception uses this register internally. curr contains the address of the fi rst buffer to be used for a packet reception and is used to restore dma pointers in the event of receive errors. this register is initialized to the same value as pstart and should not be written to again unless the controller is reset. 5.1.33 multicast address register 0 (mar0) page1 offset 08h (read/write) field name description (default = 00h) 7:0 mar0 multicast address register 0 5.1.34 multicast address register 1 (mar1) page1 offset 09h (read/write) field name description (default = 00h) 7:0 mar1 multicast address register 1 5.1.35 multicast address register 2 (mar2) page1 offset 0ah (read/write) field name description (default = 00h) 7:0 mar2 multicast address register 2 5.1.36 multicast address register 3 (mar3) page1 offset 0bh (read/write) field name description (default = 00h) 7:0 mar3 multicast address register 3 5.1.37 multicast address register 4 (mar4) page1 offset 0ch (read/write) field name description (default = 00h) 7:0 mar4 multicast address register 4 5.1.38 multicast address register 5 (mar5) page1 offset 0dh (read/write) field name description (default = 00h) 7:0 mar5 multicast address register 5 5.1.39 multicast address register 6 (mar6) page1 offset 0eh (read/write) field name description (default = 00h) 7:0 mar6 multicast address register 6 5.1.40 multicast address register 7 (mar7) page1 offset 0fh (read/write) field name description (default = 00h) 7:0 mar7 multicast address register 7
asix electronics corporation 45 AX88196BLF 5.1.41 total receive buffer free page register (tfp) page2 offset 0ah (read) field name description (default = 7fh) 7:0 tfp indicate total free page in receive buffer ri ng. a default value 7fh after hardware / software reset. it will be update the real fr ee page when every frame received. 5.1.42 receive configuration register (rcr) page2 offset 0ch (read) field name description (default = 00h) 7:0 rcr reference page0 offset 0ch for bits deifications. 5.1.43 transmit configuration register (tcr) page2 offset 0dh (read) field name description (default = 00h) 7:0 tcr reference page0 offset 0dh for bits deifications. 5.1.44 data configuration register (dcr) page2 offset 0eh (read) field name description (default = 00h) 7:0 dcr reference page0 offset 0eh for bits deifications. 5.1.45 interrupt mask register (imr) page2 offset 0fh (read) field name description (default = 00h) 7:0 imr reference page0 offset 0fh for bits deifications.
asix electronics corporation 46 AX88196BLF 5.1.46 wakeup frame byte mask (wfbm0) page3 offset 01h (read/write) field name description (default = 00h) 31:0 wfbm0 byte mask for wake-up frame filter 0. host continue write 4 times to completed 32-bits of byte mask 0. 5.1.47 wakeup frame byte mask (wfbm1) page3 offset 02h (read/write) field name description (default = 00h) 31:0 wfbm1 byte mask for wake-up frame filter 1. host continue write 4 times to completed 32-bits of byte mask 1. 5.1.48 wakeup frame byte mask (wfbm2) page3 offset 03h (read/write) field name description (default = 00h) 31:0 wfbm2 byte mask for wake-up frame filter 2. host continue write 4 times to completed 32-bits of byte mask 2. 5.1.49 wakeup frame byte mask (wfbm3) page3 offset 04h (read/write) field name description (default = 00h) 31:0 wfbm3 byte mask for wake-up frame filter 3. host continue write 4 times to completed 32-bits of byte mask 3. 5.1.50 wakeup frame 1,0 crc (wf10crc) page3 offset 05h (read/write) field name description (default = 00h) 7:0 wf0_0crc byte mask crc for wake-up frame filter 0. host continue write 4 times to completed 32-bits of byte mask 1 crc and byte mask 0 crc. crc-16 polynomials = x^16 + x^15 + x^2 + 1 15:8 wf0_1crc byte mask crc for wake-up frame filter 0. 23:16 wf1_0crc byte mask crc for wake-up frame filter 1. 31:24 wf1_1crc byte mask crc for wake-up frame filter 1. 5.1.51 wakeup frame 3,2 crc (wf32crc) page3 offset 06h (read/write) field name description (default = 00h) 7:0 wf2_0crc byte mask crc for wake-up frame filter 2. host continue write 4 times to completed 32-bits of byte mask 3 crc and byte mask 2 crc. crc-16 polynomials = x^16 + x^15 + x^2 + 1 15:8 wf2_1crc byte mask crc for wake-up frame filter 2. 23:16 wf3_0crc byte mask crc for wake-up frame filter 3. 31:24 wf3_1crc byte mask crc for wake-up frame filter 3.
asix electronics corporation 47 AX88196BLF 5.1.52 wakeup frame offset (wfofst) page3 offset 07h (read/write) field name description (default = 00h) 7:0 wf0ofst byte mask offset for wake-up frame filter 0. host continue write 4 times to completed 32-bits of byte mask 3, 2, 1, 0 offset. the unit is 16-bit. (2bytes) 15:8 wf1ofst byte mask offset for wake-up frame filter 1. 23:16 wf2ofst byte mask offset for wake-up frame filter 2. 31:24 wf3ofst byte mask offset for wake-up frame filter 3. 5.1.53 wakeup frame last byte (wflb) page3 offset 08h (read/write) field name description (default = 00h) 7:0 wflb0 mask last byte for wake-up frame filter 0. host continue write 4 times to completed 32-bits of last byte of 3, 2, 1, 0 filter. 15:8 wflb1 mask last byte for wake-up frame filter 1. 23:16 wflb2 mask last byte for wake-up frame filter 2. 31:24 wflb3 mask last byte for wake-up frame filter 3. 5.1.54 wakeup frame command (wfcmd) page3 offset 09h (read/write) field name description (default = 00h) 3:0 wfcmd0 byte mask command for wake-up frame filter 0. host continue write 4 times to completed 32-bits of byte mask command of 3, 2, 1, 0 filter and mask cascade commend. bit0: wake-up frame filter enable bit1: destination match enable bit2: multicast match enable bit3: reserved 7:4 wfcmd1 byte mask command for wake-up frame filter 1. 11:8 wfcmd2 byte mask command for wake-up frame filter 2. 15:12 wfcmd3 byte mask command for wake-up frame filter 3. 19:16 wfcscd byte mask cascade command for wake-up frame filter bit-0: cascade wake-up filter 1 and 0 bit-1: cascade wake-up filter 2 and 1 bit-2: cascade wake-up filter 3 and 2 31:18 - reserved. always zero.
asix electronics corporation 48 AX88196BLF 5.1.55 wakeup control and status register (wucsr) page3 offset 0ah (read/write) field name description (default = 00h) 7 - reserved 6 lsc link status change event flag. this bit will be clear when host write pmr or set this bit. 5 wufr wake-up frame received event flag. this bit will be clear when host write pmr or set this bit. 4 mpr magic packet received event flag. this bit will be clear when host write pmr or set this bit. 3 - reserved 2 lscwe link status change wakeup enable 0: disable (default) 1: enable 1 wuen wake-up frame enable 0: disable (default) 1: enable 0 mpen magic packet wake-up enables. 0: disable (default) 1: enable
asix electronics corporation 49 AX88196BLF 5.1.56 power management register (pmr) page3 offset 0bh (read/write) field name description (default = 00h) 7:5 - reserved 4 regstb 0: regulator in normal mode (default) 1: regulator in standby mode 3:2 - reserved 1:0 pmm power management mode, self clear when wake-up 00: normal operation (default) 01: d1 power saving. supported link status change, wake-up and magic frame for remote wake-up 10: d2 power saving. only write host wake-up register (offset 1fh) to leave d2 state. 11: reserved. do not set this mode. 5.1.57 reload eeprom register (reer) page3 offset 0ch (write) field name description 7:1 - reserved 0 reer reload eeprom host set this bit to active reload eeprom process. and it will auto clear by it self. 5.1.58 misc. control register (misc) page3 offset 0dh (write/read) field name description (default = 00h) 7:3 - reserved 2 gpte general purpose timer enable 0: disable (default) 1: enable 1 bcb1 burst cycle base on sa1 or sa0 0: base on sa0 (default) 1: base on sa1 0 tbr transmit buffer ring enable 0: remote dma write can write any where of embedded memory. (default) 1: remote dma write transmit buffer as a ring from page 40h to pstart ?1. 5.1.59 general purpose timer0 register (gpt0) page3 offset 0eh (write/read) field name description (default = ffh) 7:0 - general purpose timer [7:0] 5.1.60 general purpose timer1 register (gpt1) page3 offset 0fh (write/read) field name description (default = ffh) 7:0 - general purpose timer [15:8]
asix electronics corporation 50 AX88196BLF 5.1.61 data port (dp) offset 10h (read/write) field name description (default = 00h) 15:8 dp data port high byte 7:0 dp data port low byte 5.1.62 inter-frame gap segment 1(ifgs1) offset 12h (read/write) field name description (default = 0ch) 7 - reserved 6:0 ifgs1 inter-frame gap segment 1. 5.1.63 inter-frame gap segment 2(ifgs2) offset 13h (read/write) field name description (default = 12h) 7 - reserved 6:0 ifgs2 inter-frame gap segment 2. 5.1.64 mii/eeprom management register (memr) offset 14h (read/write) field name description (default = 00h) 7 eeck eeck eeprom clock. it output to pin-20 6 eeo eeo: (read only) eeprom data out value. it reflects pin-19 eedio value. 5 eei eei eeprom data in. it output to pin-19 eedio as eeprom data input value. 4 eecs eecs eeprom chip select. it output to pin-21 3 mdo mdo mii data out. it connects to internal phy of mdo. 2 mdi mdi (read only) mii data in. it connects to internal phy of mdi. 1 mdir signal direction: for both of smi (mdio) and eeprom (eedio) 0: output direction, mdio and eedio as push-pull drive out 1: input direction, mdio and eedio as z state for source from external signals 0 mdc mdc mii clock. it connect to internal phy of mdc
asix electronics corporation 51 AX88196BLF 5.1.65 i/o buffer type configure register (btcr) offset 15h (read/write) field name description (default = 00h) 7 - always write zero 6 pme_iqr_en pme interrupt enable 0: pme interrupt disable (default) 1: pme interrupt enable 5 irq_type interrupt i/o buffer type 0: enable irq to function as an open-drain buffer for use in a wired-or interrupt configuration. and ignored intp field, the interrupt output is always active low. (default) 1: irq output is a push-pull driver 4 irq_pol interrupt polarity 0: low active (default) 1: high active 3 - reserved 2 pme_ind pme indication 0: a static signal active when de tect wake-up event. (default) 1: a 60ms pulse active when detect wake-up event. 1 pme_type pme i/o type. when cleared, pme_pol is ignored, and the output is always active low. 0: pme to function as an open-grain buffer for use in a wired-or configuration. (default) 1: pme output is a push-pull driver. 0 pme_pol pme polarity. 0: pme active low (default) 1: pme active high (ignore when pme_type is low) mpen (cr page3 offset 0ah) enb pme logic pme_pol (offset 15h) pme_type (offset 15h) wuen (cr page3 offset 0ah) magic packet detect event wakeup frame detect event enb logic ireq irq_type (offset 15h) irq_pol (offset 15h) system interrupt event pme_irq_en (offset 15h) irq_type (from eeprom) irq_pol (from eeprom) pme_ind (offset 15h) 60ms
asix electronics corporation 52 AX88196BLF 5.1.66 inter-frame gap (ifg) offset 16h (read/write) field name description (default = 15h) 7 - reserved, always zero. inter-frame gap for back-to-back transmission without collision ifg bit-time of frame gap 15h ? n 96 ? (4*n) 15h (default) 96 6:0 ifg 15h + n 96 + (4*n) 5.1.67 back-pressure jam limit count (bjlc) offset 17h (write) field name description 7:6 - reserved, always zero. 5:0 bjlc back-pressure jam limit count, default value is 19h. 5.1.68 device status register (dsr) offset 17h (read) field name description 7 b_endian when set indicates big-endian mode. (t he big-endian register?s value not all zero) 6 rdma_rdy remote dma completed. it is same as isr bit 6. when set, it indicates the remote dma process was completed. 5 rd_rdy read data port ready, when set, indi cates data was ready from sram to data port for host reading. 4 d_rdy device ready. when set, this bit indicat es that ax88196b is ready to be accessed. this register can be read when ax88196b in any power management mode. when cleared, indicate ax88196b in reset, power saving or load eeprom state. 3 - always zero 2 i_speed phy link speed: 0: indicate the link speed is 10mb/s 1: indicate the link speed is 100mb/s 1 i_duplex phy duplex mode: 0: half-duplex 1: full-duplex 0 i_link link status: 0: link off 1: link up 5.1.69 max frame size register (mfsr0) offset 18h (read/write) field name description (default = 00h) 7:0 mfsr0 max frame size [7:0], default {mfsr1, mfsr0} = 1536 bytes 5.1.70 max frame size register (mfsr1) offset 19h (read/write) field name description (default = 06h) 7:3 - reserved 2:0 mfsr1 max frame size [10:8]
asix electronics corporation 53 AX88196BLF 5.1.71 flow control register (fcr) offset 1ah (read/write) field name description (default = 07h) 7 flwc flow-control 0: flow-control disable (default) 1: flow-control enable 6 bpen back pressure in hal f-duplex flow-control (ax88196b will ignore this bit when running at full-duplex mode) 0: back pressure disable (default) 1: back pressure enable 5:0 hwpc high water free page count. default value is 7 (7 * 256 = 1792 bytes). 5.1.72 mac configure register (mcr) offset 1bh (read/write) field name description 7 dupx mac duplex mode setting when read, this bit is indicates th e real duplex setting in mac operation. 0: half-duplex 1: full-duplex when write, this duplex setting was wire or with tcr bit-7. each one goes high then configures mac as full-duplex mode. ax88196b will ignore this bit and tcr bit-7 when using internal phy. 6 bple back-pressure leakage enable when continuous of collision n times. n number is reference register 17h of back-pressure jam limit count. 0: allow flow-control leakage to avoid hub port going partition state due to too many of collision (default) 1: no flow-control leakage 5 bbtc back-to-back transmission control: 0: disable (default) 1: enable back-to-back transmission, host can continue set txp without check transmit completed host can ignore number of collisions register (ncr) 4 mpsel media select by program 0: internal phy is selected (default) 1: external mii phy is selected. 3 vlane vlan enable 0: no supported vlan frame tagged (default) 1: only accept tag frames. ax88196b will rej ect packet if tag x8100 and vid not match whit setting by host. null vid (vid = 0) is acceptable. 2 cpteff capture effect. 0: always write low (default) 1: for mac test only. force first collision of back off is 2 slot-time and second collision of back off is 0 slot time. others as normal. 1 spmac super mac. 0: always write low (default) 1: for mac test only. back-off only 0 ~ 3 slot-time 0 zerobf zero back off time. 0: always write low (default) 1: for mac test only. back off time always zeros.
asix electronics corporation 54 AX88196BLF 5.1.73 vlan id 0 register (vidr0) offset 1ch (write) field name description 7:0 vidr0 vlan id [7:0] 5.1.74 current tx end page register (ctepr) offset 1ch (read) field name description (default = 00h) 7 txcqf tx command queue full when set, indicate the tx command queue was fu ll. host must check this status before queuing next transmit page and byte count. 6:0 ctepr ax88196b will update c tepr (current tx end page) after every transmitting comp leted without collision. it is for host to conform how many free page can reuse for next transmitting. the value is from 40h to 7fh. it will be 00h when reset or stp. 5.1.75 vlan id 1 register (vidr1) offset 1dh (write) field name description 7:5 pri frame?s priority 4 cfi canonical address frame indicator 3:0 vidr1 vlan id [11:8] 5.1.76 big-endian register (ber) offset 1eh (write) field name description (default = 00h) 7:0 - all zero, (default): little-endian if not all zero means set data byte order as big-endian mode. note: this mode can be used by 32-bit big-e ndian mode of processors operating with an external 16-bit bus only. 5.1.77 host wake up register (hwur) offset 1fh (write) field name description 7:1 - reserved 0 hwake (sc) host write one to wake up ax88196b from d2 pow er saving. it will be auto clear when wake up. 5.1.78 software reset offset 1fh (read) field name description 7:0 - don?t care this read value.
asix electronics corporation 55 AX88196BLF 5.2 the embedded phy registers the mii management 16-bit register set implemented is as follows. and the following sub-section will describes each field of the registers. address name description default value 0 mr0 control 3100h 1 mr1 status 7809h 2 mr2 phy identifier 1 003bh 3 mr3 phy identifier 2 1841h 4 mr4 autonegotiation advertisement 01e1h 5 mr5 autonegotiation li nk partner ability 0000h 6 mr6 autonegotiation expansion 0000h tab - 18 the embedded phy registers key to default: reset value 1: bit set to logic one 0: bit set to logic zero x: no set value access type ro: read only rw: read or write attribute sc: self-clearing ps: value is permanently set ll: latch low lh: latch high
asix electronics corporation 56 AX88196BLF 5.2.1 mr0 -- control register bit descriptions field type description (default = 3100h) 0.15 (sw_reset) 0, rw / sc 1 = software reset 0 = normal operation 0.14 (loopback) 0, rw 1 = loop-back enabled 0 = normal operation 0.13(speed100) 1, rw 1 = 100mbits/s 0 = 10mbits/s 0.12 (nway_ena) 1, rw 1 = auto negotiation enabled. bits 8 and 13 of this register are ignored when this bit is set. 0 = auto negotiation disabled. bits 8 and 13 of this register determine the link speed and mode. 0.11 (power down) 0, rw 1 = power down 0 = normal operation 0.10 (isolate) 0, r/w 1 = isolate 0 = normal operation 0.9 (redonway) 0, rw / sc restart autonegotiation. 1 = restart auto negotiation 0 = normal operation 0.8 (full_dup) 1, rw duplex mode. 1 = full duplex operation 0 = normal operation 0.7 (coltst) 0, rw collision test. 1 = collision test enabled 0 = normal operation 0.6:0 (reserved) x, ro reserved. write as 0, read as ?don?t care?
asix electronics corporation 57 AX88196BLF 5.2.2 mr1 -- status register bit descriptions field type description (default = 7809h) 1.15 (t4able) 0, ro / ps 100base-t4 ability. this bit will always be a 0. 0 = ax88196b is not able to perform in 100base-t4 mode 1.14 (txfuldup) 1, ro /ps 100base-tx full-duplex ability. 1 = ax88196b is able to perform in 100base-tx full duplex mode 1.13 (txhafdup) 1, ro / ps 100base-tx half-duplex ability. 1 = ax88196b is able to perform in 100base-tx half duplex mode 1.12 (enfuldup) 1, ro / ps 10base-t full-duplex ability. 1 = ax88196b is able to perform in 10base-t full duplex mode 1.11 (enhafdup) 1, ro / ps 10base-t half-duplex ability. 1 = ax88196b is able to perform in 10base-t half duplex mode 1.10:7 (reserved) 0, ro reserved. write as 0, read as ?don?t care? 1.6 (mf preamble suppression) 0, ro management frame preamble suppression: 0 = ax88196b will not accept management frames with preamble suppressed. 1.5 (nwaydone) 0, ro autonegotiation complete. 1= auto negotiation process complete 0 = auto negotiation process not complete 1.4 (rem_flt) 0, ro / lh remote fault. 1 = remote fault condition detected (cleared on read or by a chip reset) 0 = no remote fault condition detected 1.3 (nwayable) 1, ro / ps autonegotiation ability. 1 = ax88196b is able to perform auto-negotiation 1.2 (lstat_ok) 0, ro / ll link status. 1 = valid link established (100mb/s or 10mb/s operation) 0 = link not established 1.1 (jabber) 0, ro / lh jabber detect. 1 = jabber condition detected 0 = no jabber condition detected 1.0 (ext_able) 1, ro / ps extended capability. 1 = extended register capable 0 = basic register capable only
asix electronics corporation 58 AX88196BLF 5.2.3 mr2 -- identification 1 registers field type description (default = 003bh) 2.15:0 (oui[3:18]) ro organizationally unique identifier. the third through the twenty-fourth b it of the oui assigned to the phy ma nufacturer by the ieee are to be placed in bits. 2.15:0 and 3.15:10. 5.2.3 mr3 ? identification 2 registers field type description (default = 1841h) 3.15:10 (oui[19:24]) ro organizationally unique identifier. the remaining 6 bits of the oui. 3.9:4 (model[5:0]) ro model number. 6-bit model number of the device. 3.3:0 (version[3:0]) ro revision number. the value of the present revision number 5.2.4 mr4 ? autonegotiation advertisement register field type description (default = 01e1h) 4.15 (next_page) 0, ro / ps next page. 0 = no next page available ax88196b does not support the next page function. 4.14 (ack) 0, ro acknowledge. 1 = link partner ability da ta reception acknowledged 0 = not acknowledged 4.13 (rem_fault) 0, rw remote fault. 1= fault condition detected and advertised 0 = no fault detected 4.12:11 (reserved) x, rw reserved. write as 0, read as ?don?t care? 4.10 (pause) 0, rw pause. 1 = pause operation is enabled for full-duplex links 0 = pause operation is not enabled 4.9 (100baset4) 0, ro / ps 100base-t4. 0 = 100base-t4 is not supported 4.8 (100baset_fd) 1, rw 100base-tx full duplex. 1 = 100base-tx full-duplex is supported by this device 0 = 100base-tx full-duplex is not supported by this device 4.7 (100basetx) 1, rw 100base-tx half duplex. 1 = 100base-tx half-duplex is supported by this device 0 = 100base-tx half-duplex is not supported by this device 4.6 (10baset_fd) r/w 10base-t full duplex. 1 = 10base-t full-duplex is supported by this phy 0 = 10base-t full-duplex is not supported by this phy 4.5 (10baset) r/w 10base-t half duplex. 1 = 10base-t half-duplex is supported by this phy 0 = 10base-t half-duplex is not supported by this phy 4.4:0 (select) [0 0001], rw selector field . reset with the value 00001 for ieee 802.3.
asix electronics corporation 59 AX88196BLF 5.2.5 mr5 ? autonegotiation link pa rtner ability (base page) register field type description (default = 0000h) 5.15 (lp_next_page) 0, ro link partner next page. 1 = link partner is next page able 0 = link partner is not next page able 5.14 (lp_ack) 0, ro link partner acknowledge. 1 = link partner reception of data word acknowledged 0 = not acknowledged 5.13 (lp_rem_fault) 0, ro remote fault. 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 5.12:11 (reserved) x, ro reserved. write as 0, read as ?don?t care? 5.10 (lp_pause) 0, ro pause. 1 = pause operation is supported by link partner 0 = pause operation is not supported by link partner 5.9 (lp_t4) 0, ro link partner 100base-t4 supports. 1 = 100base-t4 is supported by link partner 0 = 100base-t4 is not supported by link partner 5.8 (lp_ tx_fd) 0, ro 100base-tx full-duplex support. 1 = 100base-tx full-duplex is supported by link partner 0 = 100base-tx full-duplex is not supported by link partner 5.7 (lp_ tx_hd) 0, ro 100base-tx half-duplex support. 1 = 100base-tx half-duplex is supported by link partner 0 = 100base-tx half-duplex is not supported by link partner 5.6 (lp_ 10_fd) 0, ro 10base-t full-duplex support. 1 = 10base-t full-duplex is supported by link partner 0 = 10base-t full-duplex is not supported by link partner 5.5 (lp_ 10_hd) 0, ro 10base-t half-duplex support. 1 = 10base-t half-duplex is supported by link partner 0 = 10base-t half-duplex is not supported by link partner 5.4:0 (lp_select) [0 0000], ro selector field. link partner?s binary encoded protocol selector
asix electronics corporation 60 AX88196BLF 5.2.6 mr6 ? autonegotiation expansion register field type description (default = 0000h) 6.15:5 (reserved) 0, ro reserved . write as 0, read as ?don?t care? 6.4 (par_det_fault) 0, ro / lh parallel detection fault. 1 = fault detected via the parallel detection function 0 = no fault detected 6.3 (lp_next_page_ab le) 0, ro link partner next page able. 1 = link partner is next page able 0 = link partner is not next page able 6.2 (next_page_able) 0, ro / ps next page able. 0 = phy is not next page able 6.1 (page_rec) 0, ro / lh page received . 1 = new page received 0 = new page not received 6.0 (lp_nway_able) 0, ro link partner autonegotiation capable. 1 = link partner auto-negotiation supported
asix electronics corporation 61 AX88196BLF 6.0 cpu read and write functions 6.1 isa bus type access functions. isa bus read function function mode csn aen a0 rdn wrn sd[15:8] sd[7:0] standby mode h x x x x high-z high-z byte access (for all of csr except dp) l l l l l h l l h h not valid not valid even-byte odd-byte word access (only for dp and wts=1) l l l l h odd-byte even-byte isa bus write function function mode csn aen a0 rdn wrn sd[15:8] sd[7:0] standby mode h x x x x x x byte access (for all of csr except dp) l l l l l h h h l l x x even-byte odd-byte word access (only for dp and wts=1) l l l h l odd-byte even-byte 6.2 80186 cpu bus type access functions. 80186 cpu bus read function function mode csn a0 rdn wrn sd[15:8] sd[7:0] standby mode h x x x high-z high-z byte access (for all of csr except dp) l l l h l l h h not valid odd-byte even-byte not valid word access (only for dp and wts=1) l l l h odd-byte even-byte 80186 cpu bus write function function mode csn a0 rdn wrn sd[15:8] sd[7:0] standby mode h x x x x x byte access (for all of csr except dp) l l l h h h l l x odd-byte even-byte x word access (only for dp and wts=1) l l h l odd-byte even-byte
asix electronics corporation 62 AX88196BLF 6.3 mcs-51 cpu bus type access functions. 8051 bus read function function mode csn psen sa0 rdn wrn sd[15:8] sd[7:0] standby mode h x x l x x x x x x high-z high-z high-z high-z byte access l l h h l h l l h h not valid not valid even-byte odd-byte 8051 bus write function function mode csn psen sa0 rdn wrn sd[15:8] sd[7:0] standby mode h x x l x x x x x x x x x x byte access l l h h l h h h l l x x even-byte odd-byte
asix electronics corporation 63 AX88196BLF 6.5 cpu access mii serial management interface basic operation the primary function of station management is to trans fer control and status information about the phy to a management entity. this function is accomplished by t he mdc clock input from mac entity. the maximum frequency is 2.5 mhz. the internal phy address is fixed to 10h and the equivalent circuit is shown as below: fig - 9 smi connections a specific set of registers and their contents (described in tab - 20 mii management frames- field description ) defines the nature of the informat ion transferred across the mdio interf ace. frames transmitted on the mii management interface will have the frame structure shown in tab - 19 smi management frame format . the order of bit transmission is from left to right. no te that reading and writing t he management register must be completed without interruption. read/write (r/w) pre st op phyad regad ta data idle r 1. . .1 01 10 aaaaa rrrrr z0 dddddddddddddddd z w 1. . .1 01 01 aaaaa rrrrr 10 dddddddddddddddd z tab - 19 smi management frame format field descriptions pre preamble . the phy will accept frames with no preamble. this is indicated by a 1 in mr1 1, bit 6. st start of frame. the start of frame is indicated by a 01 pattern. op operation code . the operation code for a read transacti on is 10. the operation code for a write transaction is a 01. phyadd phy address . the phy address is 5 bits, allowing for 32 unique addresses. the first phy address bit transmitted and received is the msb of the a ddress. a station management entity that is attached to multiple phy entities must have prio r knowledge of the appropriate phy address for each entity. regad register address. the register address is 5 bits, allowing fo r 32 unique registers within each phy. the first register address bit transmitted a nd received is the msb of the address. ta turnaround . the turnaround time is a 2-bit time spacing between the register address field, and the data field of a frame, to avoid drive contention on mdio during a read transaction. during a write to the phy, these bits are driven to 10 by the station. during a read, the mdio is not driven during the first bit time and is driven to a 0 by the phy during the second bit time. data data . the data field is 16 bits. the first bit transm itted and received will be bit 15 of the register being addressed. idle idle condition. the idle condition on mdio is a high-impedan ce state. all three state drivers will be disabled and the phy?s pull-up resistor will pull the mdio line to logic 1. tab - 20 mii management frames- field description (internal phy) mdc mdio-out mdio-in out p u t -enn from register offset 14h mdc mdo mdi mdi r s y 0 1 pin62 mdc pin63 mdio
asix electronics corporation 64 AX88196BLF 7.0 electrical specification and timings 7.1 absolute maximum ratings description rating units vcck (core power supply) -0.3 to 2.16 v vccio (power supply for 3.3v i/o) -0.3 to 4.0 v vccio (input voltage of 3.3v i/o with 5v tolerance) -0.3 to 5.8 v storage temperature -65 to 150 c i in (d c input current ) 20 ma i out (output short circuit current) 20 ma 7.2 general operation conditions description symbol min typ max units operating temperature ta 0 70 c junction temperature tj -40 +25 +125 c supply voltage for core (vcck, vcc18a) vcc18 +1.62 +1.8 +1.98 v supply voltage (vcc3a3, vcc3io, vcc3r3) vcc3 +2.97 +3.30 +3.63 v 10base-t operation vcc3io + vcc3a3 (3.3v) - - 32 vcck + vcc18a (1.8v) - - 20 ma 100base-tx operation vcc3io + vcc3a3 (3.3v) - - 32 vcck + vcc18a (1.8v) - - 88 ma phy power down vcc3io + vcc3a3 (3.3v) - - 24 vcck + vcc18a (1.8v) - - 17 ma d2 power saving mode vcc3io + vcc3a3 (3.3v) - - 0.04 vcck + vcc18a (1.8v) - - 0.26 ma z thermal characteristics description symbol rating units thermal resistance of junction to case ? jc 19.92 c/w thermal resistance of junction to ambient ? ja 51.24 c/w 7.3 dc characteristics 7.3.1 dc characteristics of 3.3v with 5v tolerance description symbol min typ max units low input voltage vil - 0.8 v high input voltage vih 2.0 - v low output voltage vol - 0.4 v high output voltage voh 2.4 - v switch threshold vt 1.5 v schmitt trigger negative going threshold voltage vt- 0.8 1.1 v schmitt trigger positive going threshold voltage vt+ 1.6 2.0 v input pull-up resistance rpu 40 75 190 k input pull-down resistance rpd 40 75 190 k -10 1 10 ua with pull-up resistance (vin=0) -15 -45 -85 ua input leakage current with pull-down resistance(vin=vcc3i) iin 15 45 85 ua tri-state output leakage current ioz -10 1 10 ua
asix electronics corporation 65 AX88196BLF 7.3.2 power consumption device only power measurements base on 3.3v/25 c condition. item symbol operatin g at 10base-t operating at 100base-tx phy power down d2 power saving units 1 vcc3io 10 10 8 0.04 ma 2 vcc3a3 20 20 16 0 ma 3 vcc3r3 (include vcck, vcc18a) 20 88 17 0.2 ma 50 118 41 0.24 ma 4 vcc3io + vcc3a3 + vcc3r3 165 390 135 0.8 mw device only and internal phy power down but enable mii to co-work with external phy. power measurements base on 3.3v/25 c condition. and set mr0 bit-11 (power down) to force internal phy to power-down but enable mii for connecting to external phy. item symbol operating at mii 10base-t operatin g at mii 100base-tx d2 power saving units 1 vcc3io 10 10 0.04 ma 2 vcc3a3 16 16 0 ma 3 vcc3r3 (include vcck, vcc18a) 16 17 0.2 ma 42 43 0.24 ma 4 vcc3io + vcc3a3 + vcc3r3 139 142 0.8 mw mdio mdc gnd crs col c16 0.1uf c17 0.1uf u2 93c46 cs 1 sk 2 di 3 do 4 gnd 5 nc 6 nc 7 vcc 8 resetn r4 4.7k c13 0.1uf c18 0.1uf gnd y1 25.000mhz r2 1m irq c1 c15 0.1uf c2 c7 0.1uf l3 f.b. pme c10 0.1uf c12 10uf c19 10uf rxclk c6 0.1uf c5 10uf r3 12.1k 1% j1 header 1 1 c21 0.1uf r1 4.7k c8 0.1uf phy c11 0.1uf c20 0.1uf c14 0.1uf c9 10uf l2 f.b. l1 f.b. l4 f.b. + c4 22uf/16v r5 4.7k csn rdn wrn irq pme resetn sa[0..4] sd[0..15] vcc33 gnd vcc33 vcc33 rxdv vcc18 vcc18 vcc33 vcc33 vcc3a3 vcc18a vcc3io vcc3r3 vcc33 eecs eeck eedio eedio option tpi+ vcc3a3 gnd vcc18a vcc33 gnd vcc18 vcc3r3 gnd resetn gnd eedio eeck eecs pme irq vcc18 vcc3io gnd gnd sd15 sd14 tpo+ sd13 sd12 sd11 sd10 sd9 sd8 sa3 sa4 gnd vcc3io vcc18 gnd gnd sd0 sd1 sd2 sd3 gnd sd4 sd5 sd6 sd7 gnd gnd vcc18a vcc18 gnd wrn rdn csn sa0 sa1 sa2 aen tpo- rxd0 tpi- rxd1 rxd2 speed link rxd3 full crs col gnd vcc33 c3 0.1uf resetn AX88196BLF asix u1 AX88196BLF sa2 76 sa1 77 nc 78 sa0 79 nc 80 aen,psen 81 nc 82 csn 83 nc 84 rdn 85 wrn 86 iois16 87 tclk 88 test_ck_en 89 gnd 90 nc 91 vcck 92 nc 93 vcc18a 94 nc 95 xtalin 96 nc 97 xtalout 98 nc 99 gnd18a 100 sa3 75 sa4 74 txen 73 txclk 72 txd0 71 txd1 70 txd2 69 txd3 68 sa5,fifo_sel 67 vcc3io 66 vcck 65 gnd 64 mdio 63 mdc 62 gnd 61 sd0 60 sd1 59 sd2 58 sd3 57 gnd 56 sd4 55 sd5 54 sd6 53 sd7 52 gnd 51 sd8 50 sd9 49 sd10 48 sd11 47 sd12 46 sd13 45 sd14 44 sd15 43 crs 42 col 41 gnd 40 vcc3io 39 vcck 38 ireq 37 pme 36 eecs 35 eeck 34 eedio 33 rxd0 32 rxd1 31 rxd2 30 rxd3 29 gnd 28 rstn 27 i_full/col 26 rset_bg 1 nc 2 vcc3a3 3 nc 4 gnd3a3 5 nc 6 tpi+ 7 tpi- 8 vcc18a 9 tpo+ 10 tpo- 11 gnd18a 12 v18f, 13 vcc3r3 14 gnd3r3 15 nc 16 rxclk 17 nc 18 rxdv 19 nc 20 test2 21 nc 22 test1 23 i_lk/act 24 i_speed 25 txen txclk txd0 txd1 txd2 txd3 mdio rxd0 rxd1 rxd2 rxd3 mdc txen txclk txd0 txd1 txd2 txd3 rxclk rxdv
asix electronics corporation 66 AX88196BLF device and system components this is the total power consumption of ethernet connectivity solution, which includes external components supporting the ax88196b ethernet controller as shown in the schematic as below. power measurements base on 3.3v/25 c condition. item test conditions total power (typical) units 1 10base-t operation 462 mw 2 100base-tx operation 495 mw 3 cable unplug and non power saving mode 587 mw 4 d1 power saving mode at 10base-t link 448 mw 5 d1 power saving mode at 100base-tx link 468 mw 6 phy power down 140 mw 7 d2 power saving mode 0.9 mw c17 0.1uf c20 0.1uf c8 0.1uf u2 93c46 cs 1 sk 2 di 3 do 4 gnd 5 nc 6 nc 7 vcc 8 r11 1m c11 0.1uf d3 orange led r8 12.1k 1% pme resetn resetn AX88196BLF asix u1 AX88196BLF sa2 76 sa1 77 nc 78 sa0 79 nc 80 aen,psen 81 nc 82 csn 83 nc 84 rdn 85 wrn 86 iois16 87 tclk 88 test_ck_en 89 gnd 90 nc 91 vcck 92 nc 93 vcc18a 94 nc 95 xtalin 96 nc 97 xtalout 98 nc 99 gnd18a 100 sa3 75 sa4 74 txen 73 txclk 72 txd0 71 txd1 70 txd2 69 txd3 68 sa5,fifo_sel 67 vcc3io 66 vcck 65 gnd 64 mdio 63 mdc 62 gnd 61 sd0 60 sd1 59 sd2 58 sd3 57 gnd 56 sd4 55 sd5 54 sd6 53 sd7 52 gnd 51 sd8 50 sd9 49 sd10 48 sd11 47 sd12 46 sd13 45 sd14 44 sd15 43 crs 42 col 41 gnd 40 vcc3io 39 vcck 38 ireq 37 pme 36 eecs 35 eeck 34 eedio 33 rxd0 32 rxd1 31 rxd2 30 rxd3 29 gnd 28 rstn 27 i_full/col 26 rset_bg 1 nc 2 vcc3a3 3 nc 4 gnd3a3 5 nc 6 tpi+ 7 tpi- 8 vcc18a 9 tpo+ 10 tpo- 11 gnd18a 12 v18f, 13 vcc3r3 14 gnd3r3 15 nc 16 rxclk 17 nc 18 rxdv 19 nc 20 test2 21 nc 22 test1 23 i_lk/act 24 i_speed 25 j1 header 1 1 c13 1uf r5 49.9 c19 0.1uf r3 330 irq c21 10uf rdn csn irq wrn pme r2 330 vcc33 vcc33 vcc3a3 vcc18 vcc18 vcc18a vcc3io sd[0..15] sa[0..4] vcc3r3 gnd gnd c25 0.1uf r12 4.7k r6 49.9 c15 0.1uf c9 0.1uf eecs l2 f.b. eedio eedio eeck c16 0.1uf c23 0.1uf l3 f.b. d1 green led r13 4.7k c1 0.1uf r1 4.7k r7 1m c3 c10 0.1uf c2 c14 0.1uf r10 49.9 + c4 22uf/16v c22 0.1uf l4 f.b. d2 yellow led c12 0.1uf l1 f.b. y1 25.000mhz r9 49.9 r4 330 con1 lu1s041x tx+ 1 tx- 2 ct 3 nc 4 nc 5 nc 6 rx+ 7 rx- 8 s 9 s 10 option c26 0.1uf c7 0.1uf c6 0.1uf vcc33 vcc33 link full speed tpi- tpi+ gnd vcc3a3 tpo+ vcc18a gnd vcc33 vcc33 tpo- vcc3r3 vcc18 gnd gnd speed link gnd resetn full eecs eeck eedio vcc18 irq pme gnd gnd vcc3io sd13 sd14 sd15 sd11 sd12 sd8 sd9 sd10 sa4 sa3 vcc18 vcc3io gnd gnd sd1 sd0 gnd gnd sd3 sd2 sd6 sd5 sd4 gnd sd7 vcc18a gnd gnd vcc18 csn rdn wrn sa1 sa0 sa2 vcc33 vcc33 aen c5 10uf c18 10uf vcc3a3 tpo+ tpi- tpi+ tpo- c24 10uf
asix electronics corporation 67 AX88196BLF 7.4 ac timing characteristics 7.4.1 reset timing oen ih is tr s t tr s t rstn configuration signals output drive symbol description min typ. max units trst reset pulse width 200 - - us is configuration input setup to rstn rising 80 ns ih configuration input hold after rstn rising 10 ns oen output driver after rstn rising 80 ns
asix electronics corporation 68 AX88196BLF 7.4.2 isa bus access timing (1) read cycle: tof f is 16 tonis 16 tdoff tdoh tdv tdon tcycle trdh trdh trdl tah tcycle trdl tasu a en, csn, sa[5:0] rdn sd[15:0] iois16n symbol description min typ. max units tasu address setup time 0 - - ns tah address hold time 0 - - ns tonis16 iois16n valid from sa[5:0], csn and aen - - 11 ns toffis16 iois16n valid from sa[5:0], csn and aen - - 6 ns tdv data valid time from rdn - - 33* 1 35* 2 ns tdoh data output hold time 0 - - ns trdl rdn low require time 35 - - ns trdh rdn hi require time 13 - - ns tdon data buffer turn on time 0 ns tdoff data buffer turn off time 7 ns tcycle read cycle time 48 ns * 1 : base on sd bus output load 25pf * 2 : base on sd bus output load 50pf
asix electronics corporation 69 AX88196BLF (2) write cycle: toffis16 tonis16 tdh tds tcycle twrh twrh twrl tah tcycle twrl tasu csn, sa[5:0] wrn sd[15:0] iois16 symbol description min typ. max units tasu address setup time 0 - - ns tah address hold time 0 ns tonis16 iois16n valid from sa[5:0], csn and aen - - 11 ns toffis16 iois16n disable from sa[5:0], csn and aen - - 6 ns tds data stable time - - 15 ns tdh data hold time 0 - - ns twrl wrn width time 45 - - ns twrh wrn hi require time 13 - - ns tcycle write cycle time 48 - - ns
asix electronics corporation 70 AX88196BLF 7.4.3 80186 type i/o access timing (1) read cycle: tdoff tdoh tdv tdon tc y c le trdh trdh trdl tah tc y c le trdl tas u csn, sa[5:0] rdn sd[15:0] symbol description min typ. max units tasu address setup time 0 - - ns tah address hold time 0 - - ns tdv data valid time from rdn - - 33* 1 35* 2 ns tdoh data output hold time 0 - - ns trdl rdn low require time 35 - - ns trdh rdn hi require time 13 - - ns tdon data buffer turn on time 0 ns tdoff data buffer turn off time 7 ns tcycle read cycle time 48 ns * 1 : base on sd bus output load 25pf * 2 : base on sd bus output load 50pf
asix electronics corporation 71 AX88196BLF (2) write cycle tdh tds tc y c le tw rh tw rh tw rl tah tc y c le tw rl tas u csn, sa[5:0] wrn sd[15:0] symbol description min typ. max units tasu address setup time 0 - - ns tah address hold time 0 - - ns tds data stable time - - 15 ns tdh data hold time 0 - - ns twrl wrn width time 35 - - ns twrh wrn hi require time 13 - - ns tcycle write cycle time 48 - - ns
asix electronics corporation 72 AX88196BLF 7.4.4 8051 bus access timing (1) read cycle tdoff tdo h tdv tdon tcycle trdh trdh trdl tah tcycle trdl tas u psen, csn , sa [ 5 : 0 ] rdn sd[15:0] symbol description min typ. max units tasu address setup time 0 - - ns tah address hold time 0 - - ns tdv data valid time from rdn - - 33* 1 35* 2 ns tdoh data output hold time 0 - - ns trdl rdn low require time 35 - - ns trdh rdn hi require time 13 - - ns tdon data buffer turn on time 0 ns tdoff data buffer turn off time 7 ns tcycle read cycle time 48 ns * 1 : base on sd bus output load 25pf * 2 : base on sd bus output load 50pf
asix electronics corporation 73 AX88196BLF (2) write cycle tdh tds tcycle tw rh tw rh tw rl tah tcycle tw rl tas u psen, csn , sa [ 5 : 0 ] wrn sd[15:0] symbol description min typ. max units tasu address setup time 0 - - ns tah address hold time 0 - - ns tds data stable time - - 15 ns tdh data hold time 0 - - ns twrl wrn width time 35 - - ns twrh wrn hi require time 13 - - ns tcycle write cycle time 48 - - ns
asix electronics corporation 74 AX88196BLF 7.4.5 burst reads access timing burst read access is enabled when se t fifo_sel(sa5) is driven high duri ng a read access. this is normally accomplished by connecting the fifo_sel(sa5) signal to a high-order address line. this mode is useful when the host processor must increment its address when accessing the ax88196b. in this mode, performance is improved by allowing an unlimited number of back-to-back words read cycles. ax88196b base on sa0 or sa1 address toggles to identif y word access cycle time. host can set burst cycle base on sa0 or sa1 toggle by bcb1 (cr page3 offset 0dh). tdoff tdoh tadv tadv tadv tdv tdon trdh trdh tah tas u tac y c tac y c tac y c tac y c tac y c tac y c fifo_sel( sa 5) sa1 or sa0 csn, rdn sd[15:0] symbol description min typ. max units tasu address setup time 0 - - ns tah address hold time 0 - - ns tdv data valid time from rdn - - 33* 1 35* 2 ns tadv data valid time from address 33* 1 35* 2 ns tdoh data output hold time 0 - - ns trdh rdn hi require time 13 - - ns tacyc read cycle time 48 ns tdon data buffer turn on 0 ns tdoff data buffer turn off 7 ns * 1 : base on sd bus output load 25pf * 2 : base on sd bus output load 50pf
asix electronics corporation 75 AX88196BLF 7.4.6 mii timing tth tts ttcl k ttcl ttcl k ttcl ttch ttch txclk txen / txd[3:0] symbol description min typ. max units ttclk txclk clock cycle time *1 - 40.0 - ns ttch txclk clock high time *2 - 20.0 - ns ttcl txclk clock low time *2 - 20.0 - ns tts txd [3:0], txen setup to rising txclk 30 - - ns tth txd [3:0], txen hold from rising txclk 4 - - ns trh trs trc lk trc l trc lk trc l trc h trc h rxclk rxdv / rxd[3:0] symbol description min typ. max units trclk rxclk clock cycle time *1 - 40.0 - ns trch rxclk clock high time *2 - 20.0 - ns trcl rxclk clock low time *2 - 20.0 - ns trs rxd [3:0], rxdv setup to rising rxclk 4 - - ns trh rxd [3:0], rxdv hold from rising txclk 4 - - ns *1: for 10mbps, the typical value of ttclk and trclk shall scale to 400ns. *2: for 10mbps, the typical value of ttch, ttcl, trch, and trcl shall scale to 200ns.
asix electronics corporation 76 AX88196BLF 8.0 package information b e d hd e he pin 1 a2 a1 l l1 a symbol dimension (mm) min. typ max a1 0.05 0.15 a2 1.35 1.40 1.45 a 1.60 b 0.17 0.22 0.27 d 13.9 14.00 14.1 e 13.9 14.00 14.1 e 0.50 hd 15.85 16.00 16.15 he 15.85 16.00 16.15 l 0.45 0.60 0.75 l1 1.00 0 3.5 7
asix electronics corporation 77 AX88196BLF 9.0 ordering information model no description AX88196BLF 100 pin, lqfp package, commercial grade 0 c to +70 c (green, lead-free)
asix electronics corporation 78 AX88196BLF appendix a1: mcs51-like (8-bit) an example, ax88196b?s bus setting as mcs-51 mode. (two external pull- up resister connect to eecs and eeck) read write host addr a[5:0] sd[15:8] sd[7:0] ax88196b csr offset host addr a[5:0] sd[15:8] sd[7:0] ax88196b csr offset 0 offset 1 offset 0 0 0 no effect to offset 0 0 1 offset 1 offset 1 1 1 no effect to offset 1 1 2 offset 3 offset 2 2 2 no effect to offset 2 2 3 offset 3 offset 3 3 3 no effect to offset 3 3 4 offset 5 offset 4 4 4 no effect to offset 4 4 5 offset 5 offset 5 5 5 no effect to offset 5 5 6 offset 7 offset 6 6 6 no effect to offset 6 6 7 offset 7 offset 7 7 7 no effect to offset 7 7 8 offset 9 offset 8 8 8 no effect to offset 8 8 9 offset 9 offset 9 9 9 no effect to offset 9 9 a offset b offset a a a no effect to offset a a b offset b offset b b b no effect to offset b b c offset d offset c c c no effect to offset c c d offset d offset d d d no effect to offset d d e offset f offset e e e no effect to offset e e f offset f offset f f f no effect to offset f f 10 (dp) (dp) (dp) 10 no effect (dp) (dp) 11 x x x 11 x x x 12 offset 13 offset 12 12 12 no effect to offset 12 12 13 offset 13 offset 13 13 13 no effect to offset 13 13 14 offset 15 offset 14 14 14 no effect to offset 14 14 15 offset 15 offset 15 15 15 no effect to offset 15 15 16 offset 17 offset 16 16 16 no effect to offset 16 16 17 offset 17 offset 17 17 17 no effect to offset 17 17 18 offset 19 offset 18 18 18 no effect to offset 18 18 19 offset 19 offset 19 19 19 no effect to offset 19 19 1a offset 1b offset 1a 1a 1a no effect to offset 1a 1a 1b offset 1b offset 1b 1b 1b no effect to offset 1b 1b 1c offset 1d offset 1c 1c 1c no effect to offset 1c 1c 1d offset 1d offset 1d 1d 1d no effect to offset 1d 1d 1e no effect offset 1e 1e 1e no effect to offset 1e 1e 1f (reset) *1 (reset) *1 1f 1f no effect to offset 1f 1f *1 read offset 1fh re gister will reset ax88196b sa0 sa1 sd[15:8] sa2 sa3 sa4 sa5/fifo_sel aen/psen sd[7:0] rdn wrn irq a0 a1 a2 a3 a4 a5 psen data[7:0] rdn wrn int mcs-51 ax88196b
asix electronics corporation 79 AX88196BLF appendix a2: isa-like (8/16-bit) an example, ax88196b?s bus setting as isa mode. (n o external resister c onnect to eecs and eeck) csr read csr write host addr a[5:0] sd[15:8] sd[7:0] ax88196b csr offset host addr a[5:0] sd[15:8] sd[7:0] ax88196b csr offset 0 offset 1 offset 0 0 0 no effect to offset 0 0 1 offset 1 offset 1 1 1 no effect to offset 1 1 2 offset 3 offset 2 2 2 no effect to offset 2 2 3 offset 3 offset 3 3 3 no effect to offset 3 3 4 offset 5 offset 4 4 4 no effect to offset 4 4 5 offset 5 offset 5 5 5 no effect to offset 5 5 6 offset 7 offset 6 6 6 no effect to offset 6 6 7 offset 7 offset 7 7 7 no effect to offset 7 7 8 offset 9 offset 8 8 8 no effect to offset 8 8 9 offset 9 offset 9 9 9 no effect to offset 9 9 a offset b offset a a a no effect to offset a a b offset b offset b b b no effect to offset b b c offset d offset c c c no effect to offset c c d offset d offset d d d no effect to offset d d e offset f offset e e e no effect to offset e e f offset f offset f f f no effect to offset f f 10 (dp) (dp) (dp) 10 (dp) (dp) (dp) 11 x x x 11 x x x 12 offset 13 offset 12 12 12 no effect to offset 12 12 13 offset 13 offset 13 13 13 no effect to offset 13 13 14 offset 15 offset 14 14 14 no effect to offset 14 14 15 offset 15 offset 15 15 15 no effect to offset 15 15 16 offset 17 offset 16 16 16 no effect to offset 16 16 17 offset 17 offset 17 17 17 no effect to offset 17 17 18 offset 19 offset 18 18 18 no effect to offset 18 18 19 offset 19 offset 19 19 19 no effect to offset 19 19 1a offset 1b offset 1a 1a 1a no effect to offset 1a 1a 1b offset 1b offset 1b 1b 1b no effect to offset 1b 1b 1c offset 1d offset 1c 1c 1c no effect to offset 1c 1c 1d offset 1d offset 1d 1d 1d no effect to offset 1d 1d 1e no effect offset 1e 1e 1e no effect to offset 1e 1e 1f (reset) *1 (reset) *1 1f 1f no effect to offset 1f 1f *1 read offset 1fh re gister will reset ax88196b sa0 sa1 sa2 sa3 sa4 sa5/fifo_sel aen/psen sd[15:0] rdn wrn irq a0 a1 a2 a3 a4 a5 aen data[15:0] iordn iowrn int isa ax88196b
asix electronics corporation 80 AX88196BLF appendix a3: 186-like (16-bit) an example, ax88196b?s bus setting as 186 mode. (one external pull-up resister connect to eeck) read write host addr a[5:0] sd[15:8] sd[7:0] ax88196b csr offset host addr a[5:0] sd[15:8] sd[7:0] ax88196b csr offset 0 offset 1 offset 0 0 0 no effect to offset 0 0 1 offset 1 offset 0 1 1 to offset 1 no effect 1 2 offset 3 offset 2 2 2 no effect to offset 2 2 3 offset 3 offset 2 3 3 to offset 3 no effect 3 4 offset 5 offset 4 4 4 no effect to offset 4 4 5 offset 5 offset 4 5 5 to offset 5 no effect 5 6 offset 7 offset 6 6 6 no effect to offset 6 6 7 offset 7 offset 6 7 7 to offset 7 no effect 7 8 offset 9 offset 8 8 8 no effect to offset 8 8 9 offset 9 offset 8 9 9 to offset 9 no effect 9 a offset b offset a a a no effect to offset a a b offset b offset a b b to offset b no effect b c offset d offset c c c no effect to offset c c d offset d offset c d d to offset d no effect d e offset f offset e e e no effect to offset e e f offset f offset e f f to offset f no effect f 10 (dp) (dp) (dp) 10 (dp) (dp) (dp) 11 x x x 11 x x x 12 offset 13 offset 12 12 12 no effect to offset 12 12 13 offset 13 offset 12 13 13 to offset 13 no effect 13 14 offset 15 offset 14 14 14 no effect to offset 14 14 15 offset 15 offset 14 15 15 to offset 15 no effect 15 16 offset 17 offset 16 16 16 no effect to offset 16 16 17 offset 17 offset 16 17 17 to offset 17 no effect 17 18 offset 19 offset 18 18 18 no effect to offset 18 18 19 offset 19 offset 18 19 19 to offset 19 no effect 19 1a offset 1b offset 1a 1a 1a no effect to offset 1a 1a 1b offset 1b offset 1a 1b 1b to offset 1b no effect 1b 1c offset 1d offset 1c 1c 1c no effect to offset 1c 1c 1d offset 1d offset 1c 1d 1d to offset 1d no effect 1d 1e no effect offset 1e 1e 1e no effect to offset 1e 1e 1f (reset) *1 (reset) *1 1f 1f to offset 1f no effect 1f *1 read offset 1fh re gister will reset ax88196b sa0 sa1 sa2 sa3 sa4 sa5/fifo_sel aen/psen sd[15:0] rdn wrn irq a0 a1 a2 a3 a4 a5 data[15:0] rdn wrn int 16-bit processor ax88196b
asix electronics corporation 81 AX88196BLF appendix a4: co-work with 32-bit processor an example, ax88196b co-work with samsung 2440 processor. (32-bit processor with external 16-bit bus) ax88196b?s bus setting as isa mode. (wit hout external resister connect to eecs and eeck) host can use burst read mode, where the host proce ssor increments its address when reading ax88196b received data. ax88196b supports two kinds of data port for receivi ng/transmitting packets from/to ax88196b. one is the pio data port (offset 10h); the other one is the sram -like data port (e.g. offset 800h ~ fffh for samsung2440 processor as described in below figure). the sram-like da ta port address range depends on which address line of host processor is being connected to the address line sa5/fifo_sel of ax88196b. software on host cpu can issue single data read/write command to both pio data port and sram-like data port. however, to use burst data read/write commands, one has to use sram-like data port, which requires sa5/fifo_sel (pin 45) of ax88196b connecting to an upper address line of host cpu. ax88196b with samsung 2440 processor reference schematic has sa5/fifo_sel pin connected to upper address line (i.e. a11 of samsung 2440) for supporting burst data read/write commands. read write host addr a[11:0] sd[15:8] sd[7:0] ax88196b csr offset host addr a[11:0] sd[15:8] sd[7:0] ax88196b csr offset 0 offset 1 offset 0 0 0 no effect to offset 0 0 2 offset 1 offset 1 1 2 no effect to offset 1 1 4 offset 3 offset 2 2 4 no effect to offset 2 2 6 offset 3 offset 3 3 6 no effect to offset 3 3 8 offset 5 offset 4 4 8 no effect to offset 4 4 a offset 5 offset 5 5 a no effect to offset 5 5 c offset 7 offset 6 6 c no effect to offset 6 6 e offset 7 offset 7 7 e no effect to offset 7 7 10 offset 9 offset 8 8 10 no effect to offset 8 8 12 offset 9 offset 9 9 12 no effect to offset 9 9 14 offset b offset a a 14 no effect to offset a a 16 offset b offset b b 16 no effect to offset b b 18 offset d offset c c 18 no effect to offset c c 1a offset d offset d d 1a no effect to offset d d 1c offset f offset e e 1c no effect to offset e e 1e offset f offset f f 1e no effect to offset f f 20 10 (dp) 10 (dp) 10 (dp) 20 10 (dp) 10 (dp) 10 (dp) 22 x x x 22 x x x 24 offset 13 offset 12 12 24 no effect to offset 12 12 26 offset 13 offset 13 13 26 no effect to offset 13 13 28 offset 15 offset 14 14 28 no effect to offset 14 14 2a offset 15 offset 15 15 2a no effect to offset 15 15 2c offset 17 offset 16 16 2c no effect to offset 16 16 2e offset 17 offset 17 17 2e no effect to offset 17 17 a0 a1 a2 a3 a4 a5/fifo_sel csn rdn wrn irq aen/psen a0 a1 a2 a3 a4 a5 a11 csn rdn wrn int samsung2440 ax88196b
asix electronics corporation 82 AX88196BLF 30 offset 19 offset 18 18 30 no effect to offset 18 18 32 offset 19 offset 19 19 32 no effect to offset 19 19 34 offset 1b offset 1a 1a 34 no effect to offset 1a 1a 36 offset 1b offset 1b 1b 36 no effect to offset 1b 1b 38 offset 1d offset 1c 1c 38 no effect to offset 1c 1c 3a offset 1d offset 1d 1d 3a no effect to offset 1d 1d 3c no effect offset 1e 1e 3c no effect to offset 1e 1e 3e (reset) *1 (reset) *1 1f 3e no effect to offset 1f 1f 40 ~7ff no used no used no used 40 ~7ff no used no used no used 800 ~ fff (dp) (dp) 10 (dp) 800 ~ fff (dp) (dp) 10 (dp) *1 read offset 1fh register will reset ax88196b
asix electronics corporation 83 AX88196BLF appendix a5: big-endian processor of data byte lands an example, ax88196b co-work with big-endian processor like renesas h8/sh2 mcu, etc.. (to support big-endian processors, the hardware designer must explicitly swap the connection of data byte lanes.) addr d[7:0] d[15:8] csn rdn wrn irq add r d[7:0] d[15:8] csn rdn wrn int big-endian processor ax88196b
asix electronics corporation 84 AX88196BLF appendix b: disable ax88196b voltage regulator ax88196b integrates an on-chip 3.3v to 1.8v voltage regulator for single-power supply system design. if the system have 1.8v power source already, user may like to disable ax88196b voltage regulator and use the existing 1.8v power source (probably a higher efficiency version). in that case, user can connect vcc3r3 (pin-14) and gnd3r3 (pin-15) to ground, keep v18f (pin-13) open, and set regstb bit of pmr register (page3 offset 0bh) to 0 (i.e. logic "low") to avoid the leakage cu rrent. please refer to belo w picture for details. note: if user connects the vcc3r3 to 3.3v vcc and wants to disable the internal voltage regulator of ax88196b, the regstb bit of pmr register should be set to 1 to set the regulator in standby mode to reduce the leakage current. ax88196b v18f regstb vcc18a vcc k vcc3r3 gnd3r3 keep nc without loading supply analog 1.8v from existing power source on system supply digital 1.8v from existing power source on system logic ?low?
asix electronics corporation 85 AX88196BLF reversion history revision date comment v1.0 2006/08/05 initial release. v1.1 2007/3/21 1. add us patent approved (no 6799231) in the features page. 2. change the product name in the features page. 3. update ax88196b block diagram in section 1.2. 4. modify the wake-up configuration descriptions in section 4.3.1. v1.2 2007/4/28 1. modify the description of sa5/fifo_sel pin in section 2.1 and appendix a4. 2. swapped the pin name of xtal in and xtalout in section 2.5 and figure 2. v1.3 2007/8/18 1. add some information into section 7.2.
asix electronics corporation 86 AX88196BLF 4f, no.8, hsin ann rd., hsinchu science park, hsinchu, taiwan, r.o.c. tel: +886-3-5799500 fax: +886-3-5799558 email: support@asix.com.tw web: http:// www.asix.com.tw

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